SLVSEI1C June   2019  – October 2020 TPS62864 , TPS62866

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C InterfaceTiming Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Save Mode
      2. 8.3.2 Forced PWM Mode
      3. 8.3.3 Start-up
      4. 8.3.4 Switch Current Limit and HICCUP Short-Circuit Protection
      5. 8.3.5 Undervoltage Lockout (UVLO)
      6. 8.3.6 Thermal Warning and Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable (EN)
      2. 8.4.2 Output Discharge
      3. 8.4.3 Start-up Output Voltage and I2C Slave Address Selection (VSET)
      4. 8.4.4 Select Output Voltage Registers (VID)
      5. 8.4.5 Power Good (PG)
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 HS-Mode Protocol
      4. 8.5.4 I2C Update Sequence
      5. 8.5.5 I2C Register Reset
    6. 8.6 Register Map
      1. 8.6.1 Slave Address Byte
      2. 8.6.2 Register Address Byte
      3. 8.6.3 VOUT Register 1
      4. 8.6.4 VOUT Register 2
      5. 8.6.5 CONTROL Register
      6. 8.6.6 STATUS Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 6-A Output Current Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Setting The Output Voltage
          3. 9.2.1.2.3 Output Filter Design
          4. 9.2.1.2.4 Inductor Selection
          5. 9.2.1.2.5 Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Smaller Application Solution
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Support Resources
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7.6 I2C InterfaceTiming Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
f(SCL) SCL Clock Frequency Standard mode 100 kHz
Fast mode 400 kHz
Fast mode plus 1 MHz
High-speed mode (write operation), CB – 100 pF max 3.4 MHz
High-speed mode (read operation), CB – 100 pF max 3.4 MHz
High-speed mode (write operation), CB – 400 pF max 1.7 MHz
High-speed mode (read operation), CB – 400 pF max 1.7 MHz
tBUF Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
tHD, tSTA Hold Time (Repeated) START condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tLOW LOW Period of the SCL Clock Standard mode 4.7 µs
Fast mode 1.3 µs
Fast mode plus 0.5 µs
High-speed mode, CB – 100 pF max 160 ns
High-speed mode, CB – 400 pF max 320 ns
tHIGH HIGH Period of the SCL Clock Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode, CB – 100 pF max 60 ns
High-speed mode, CB – 400 pF max 120 ns
tSU, tSTA Setup Time for a Repeated START Condition Standard mode 4.7 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tSU, tDAT Data Setup Time Standard mode 250 ns
Fast mode 100 ns
Fast mode plus 50 ns
High-speed mode 10 ns
tHD, tDAT Data Hold Time Standard mode 0 3.45 µs
Fast mode 0 0.9 µs
Fast mode plus 0 µs
High-speed mode, CB – 100 pF max 0 70 ns
High-speed mode, CB – 400 pF max 0 150 ns
tRCL Rise Time of SCL Signal Standard mode 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100 pF max 10 40 ns
High-speed mode, CB – 400 pF max 20 80 ns
tRCL1 Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Standard mode 20 + 0.1 CB 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100 pF max 10 80 ns
High-speed mode, CB – 400 pF max 20 160 ns
tFCL Fall Time of SCL Signal Standard mode 20 + 0.1 CB 300 ns
Fast mode 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100 pF max 10 40 ns
High-speed mode, CB – 400 pF max 20 80 ns
tRDA Rise Time of SDA Signal Standard mode 1000 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100 pF max 10 80 ns
High-speed mode, CB – 400 pF max 20 160 ns
tFDA Fall Time of SDA Signal Standard mode 300 ns
Fast mode 20 + 0.1 CB 300 ns
Fast mode plus 120 ns
High-speed mode, CB – 100 pF max 10 80 ns
High-speed mode, CB – 400 pF max 20 160 ns
tSU, tSTO Setup Time of STOP Condition Standard mode 4 µs
Fast mode 600 ns
Fast mode plus 260 ns
High-Speed mode 160 ns
CB Capacitive Load for SDA and SCL Standard mode 400 pF
Fast mode 400 pF
Fast mode plus 550 pF
High-Speed mode 400 pF