SLVSEK5A August 2018 – October 2018 TPS7B70-Q1
PRODUCTION DATA.
The power-good delay, t(DLY), is the time from when PGADJ is greater than V(PG,REF) until the PG pin goes high. The power-good delay is a function of the value of the external capacitor that is connected to the DELAY pin (CDELAY). Connecting an external capacitor from this pin to GND sets the power-good delay. The constant current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator, and Equation 2 determines the power-good delay. Figure 22 illustrates a timing diagram for power-good power-up conditions.
where
If the DELAY pin is open, the default delay time is t(DLY_FIX).