SLVSEK5A August   2018  – October 2018 TPS7B70-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Enable (EN)
      2. 7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)
      3. 7.3.3 Adjustable Power-Good Delay Timer (DELAY)
      4. 7.3.4 Undervoltage Shutdown
      5. 7.3.5 Current Limit
      6. 7.3.6 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With Input Voltage Less Than 4 V
      2. 7.4.2 Operation With Input Voltage Greater Than 4 V
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
        3. 8.2.2.3 Power-Good Threshold
        4. 8.2.2.4 Power-Good Delay, t(DLY)
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP With PowerPAD
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DELAY 8 O Power-good delay adjustment pin. Connect this pin through a capacitor to ground to adjust the power-good delay time.
EN 2 I Device enable pin. Pull this pin down to low-level voltage to disable the device. Pull this pin up to high-level voltage to enable the device.
GND 3, 4, 5, 6, 7, 9, 10, 12, 13 — Ground reference
IN 1 I Device input power supply pin
OUT 16 O Device 3.3-V or 5-V regulated output-voltage pin
PG 14 O Power-good pin. Open-drain output pin. Pull this pin up to VOUT or to a reference through a resistor. When the output voltage is not ready, this pin is pulled down to ground.
PGADJ 15 O Power-good threshold-adjustment pin. Connect a resistor divider between the PGADJ and OUT pins to set the power-good threshold. Connect this pin to ground to set the threshold to 91.6% of output voltage VOUT.
VINT 11 I Internal voltage rail. Tie this pin above 2 V for lowest IGND.
PowerPAD — — Solder thermal pad to board to improve the thermal performance.