SLVSEO1A August   2021  – May 2022 ADC08DJ5200RF

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Comparison
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3 ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4 Temperature Monitoring Diode
      5. 7.3.5 Timestamp
      6. 7.3.6 Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7 Programmable FIR Filter (PFIR)
        1. 7.3.7.1 Dual Channel Equalization
        2. 7.3.7.2 Single Channel Equalization
        3. 7.3.7.3 Time Varying Filter
      8. 7.3.8 JESD204C Interface
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Scrambler
        3. 7.3.8.3 Link Layer
        4. 7.3.8.4 8B/10B Link Layer
          1. 7.3.8.4.1 Data Encoding (8B/10B)
          2. 7.3.8.4.2 Multiframes and the Local Multiframe Clock (LMFC)
          3. 7.3.8.4.3 Code Group Synchronization (CGS)
          4. 7.3.8.4.4 Initial Lane Alignment Sequence (ILAS)
          5. 7.3.8.4.5 Frame and Multiframe Monitoring
        5. 7.3.8.5 64B/66B Link Layer
          1. 7.3.8.5.1 64B/66B Encoding
          2. 7.3.8.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
          3. 7.3.8.5.3 Block, Multiblock and Extended Multiblock Alignment using Sync Header
            1. 7.3.8.5.3.1 Cyclic Redundancy Check (CRC) Mode
            2. 7.3.8.5.3.2 Forward Error Correction (FEC) Mode
          4. 7.3.8.5.4 Initial Lane Alignment
          5. 7.3.8.5.5 Block, Multiblock and Extended Multiblock Alignment Monitoring
        6. 7.3.8.6 Physical Layer
          1. 7.3.8.6.1 SerDes Pre-Emphasis
        7. 7.3.8.7 JESD204C Enable
        8. 7.3.8.8 Multi-Device Synchronization and Deterministic Latency
        9. 7.3.8.9 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 Clock Upset Detection
        2. 7.3.9.2 FIFO Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 Dual-Input Single-Channel Mode (DUAL DES Mode)
      4. 7.4.4 JESD204C Modes
        1. 7.4.4.1 JESD204C Operating Modes Table
        2. 7.4.4.2 JESD204C Modes continued
        3. 7.4.4.3 JESD204C Transport Layer Data Formats
        4. 7.4.4.4 64B/66B Sync Header Stream Configuration
      5. 7.4.5 Power-Down Modes
      6. 7.4.6 Test Modes
        1. 7.4.6.1 Serializer Test-Mode Details
        2. 7.4.6.2 PRBS Test Modes
        3. 7.4.6.3 Clock Pattern Mode
        4. 7.4.6.4 Ramp Test Mode
        5. 7.4.6.5 Short and Long Transport Test Mode
          1. 7.4.6.5.1 Short Transport Test Pattern
        6. 7.4.6.6 D21.5 Test Mode
        7. 7.4.6.7 K28.5 Test Mode
        8. 7.4.6.8 Repeated ILA Test Mode
        9. 7.4.6.9 Modified RPAT Test Mode
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 SPI Register Map
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Reconfigurable Dual-Channel 5-GSPS or Single-Channel 10-Gsps Oscilloscope
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
          3. 8.2.1.1.3 ADC08DJ5200RF
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 123
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.4.4 JESD204C Modes

The ADC08DJ5200RF can be programmed as a single-channel or dual-channel ADC and a number JESD204C output formats. Table 7-14 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.

Table 7-14 ADC08DJ5200RF Operating Mode Configuration Parameters
PARAMETER DESCRIPTION USER CONFIGURED OR DERIVED VALUE
JMODE JESD204C operating mode, automatically derives the rest of the JESD204C parameters, single-channel or dual-channel mode User configured Set by JMODE (see the JESD204C mode register)
DES 1 = single-channel mode, 0 = dual-channel mode Derived See Operating Modes
R Number of bits transmitted per lane per CLK± cycle. The JESD204C line rate is the CLK± frequency times R. This parameter sets the SerDes PLL multiplication factor or controls bypassing of the SerDes PLL. Derived See Operating Modes
Links Number of JESD204C links used Derived See Operating Modes
K Number of frames per multiframe (8B/10B mode) User configured Set by KM1 (see the JESD204C K parameter register), see the allowed values in Operating Modes. This parameter is ignored in 64B/66B modes.
E Number of multiblocks per extended multiblock (64B/66B mode) Derived Always set to '1' in ADC08DJ5200RF. This parameter is ignored in 8B/10B modes.

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the ILAS, however the transport layer uses the same parameters. In the ADC08DJ5200RF, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 7-15 describes these parameters.

Table 7-15 JESD204C Initial Lane Alignment Sequence Parameters
PARAMETERDESCRIPTIONUSER CONFIGURED OR DERIVEDVALUE
ADJCNTLMFC adjustment amount (not applicable)DerivedAlways 0
ADJDIRLMFC adjustment direction (not applicable)DerivedAlways 0
BIDBank IDDerivedAlways 0
CFNumber of control words per frameDerivedAlways 0
CSControl bits per sampleDerivedAlways set to 0 in ILAS, see Operating Modes for actual usage
DIDDevice identifier, used to identify the linkUser configuredSet by DID (see the JESD204C DID parameter register), see Lane Assignments
FNumber of octets (bytes) per frame (per lane)DerivedSee Operating Modes
HDHigh-density format (samples split between lanes)DerivedAlways 0
JESDVJESD204 standard revisionDerivedAlways 1
KNumber of frames per multiframeUser configuredSet by the KM1 register, see the JESD204C K parameter register
LNumber of serial output lanes per linkDerivedSee Operating Modes
LIDLane identifier for each laneDerivedSee Lane Assignments
MNumber of converters used to determine lane bit packing; may not match number of ADC channels in the deviceDerivedSee Operating Modes
NSample resolution (before adding control and tail bits)DerivedSee Operating Modes
N'Bits per sample after adding control and tail bitsDerivedSee Operating Modes
SNumber of samples per converter (M) per frameDerivedSee Operating Modes
SCRScrambler enabledUser configuredSet by the JESD204C control register
SUBCLASSVDevice subclass versionDerivedAlways 1
RES1Reserved field 1DerivedAlways 0
RES2Reserved field 2DerivedAlways 0
CHKSUMChecksum for ILAS checking (sum of all above parameters modulo 256)DerivedComputed based on parameters in this table