SLVSES4D September   2019  – June 2024 TPS54J060

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Enable and Internal LDO
      2. 6.3.2  Split Rail and External LDO
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Soft Start and Output-Voltage Tracking
      5. 6.3.5  Frequency and Operation Mode Selection
      6. 6.3.6  D-CAP3™ Control Mode
      7. 6.3.7  Current Sense and Positive Overcurrent Protection
      8. 6.3.8  Low-side FET Negative Current Limit
      9. 6.3.9  Power Good
      10. 6.3.10 Overvoltage and Undervoltage Protection
      11. 6.3.11 Out-Of-Bounds Operation (OOB)
      12. 6.3.12 Output Voltage Discharge
      13. 6.3.13 UVLO Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Pre-Bias Start-up
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 7.2.2.2  Choose the Output Inductor (L)
        3. 7.2.2.3  Set the Current Limit (TRIP)
        4. 7.2.2.4  Choose the Output Capacitors (COUT)
        5. 7.2.2.5  Choose the Input Capacitors (CIN)
        6. 7.2.2.6  Feedback Network (FB Pin)
        7. 7.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 7.2.2.8  EN Pin Resistor Divider
        9. 7.2.2.9  VCC Bypass Capacitor
        10. 7.2.2.10 BOOT Capacitor
        11. 7.2.2.11 Series BOOT Resistor and RC Snubber
        12. 7.2.2.12 PGOOD Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Ordering Information

7.4.1 Layout Guidelines

Before beginning a design using the device, consider the following:

  • A 0402-sized 0.01-µF to 0.1-µF decoupling capacitor must be placed as close as possible to the VIN and PGND pins to decouple high frequency noise and help reduce switch node ringing. Larger VIN decoupling capacitors must be placed as close as possible to VIN and PGND pins behind this capacitor to further minimize the input AC-current loop.
  • Place the power components (including input and output capacitors, the inductor, and the IC) on the solder side of the PCB. In order to shield and isolate the small signal traces from noisy power lines, insert and connect at least one inner plane to ground.
  • All sensitive analog traces and components such as FB, PGOOD, TRIP, MODE, and SS/REFIN must be placed away from high-voltage switching nodes such as SW and BOOT to avoid coupling. Use internal layers as ground planes and shield the feedback trace from power traces and components.
  • Place the feedback resistor near the device to minimize the FB trace distance.
  • Place the OCP-setting resistor (RTRIP) and mode-setting resistor (RMODE) close to the device. Use the common AGND via to connect the resistors to the VCC PGND plane if applicable.
  • Place the VCC decoupling capacitors as close as possible to the device. If multiple capacitors are used, provide PGND vias for each decoupling capacitor and ensure the return path is as small as possible.
  • Keep the switch node connections from pins 2 and 11 to the inductor as short and wide as possible.
  • Use separate traces to connect SW node to the bootstrap capacitor and RC snubber, if used, instead of combining them into one connection. Keep both the BOOT and snubber paths short for low inductance and the best possible performance. Also, to minimize inductance, avoid using vias for the RC snubber routing and use very wide traces. To be most effective, the RC snubber must be connected between a large SW copper shape and large PGND copper shape on the same side of the PCB as the TPS54J060.
  • Avoid connecting AGND to the PCB ground plane (PGND) in a high current path where significant IR and L*dI/dt drops can occur.