SLVSES4D September 2019 – June 2024 TPS54J060
PRODUCTION DATA
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1, 14 | PGND | G | Power ground of internal low-side MOSFET |
2., 11 | SW | O | Output switching terminal of the power converter. Connect this pin to the output inductor. |
3 | VIN | I | Power-supply input pins for both integrated power MOSFET pair and the internal regulator. Place the decoupling input capacitors as close as possible to VIN pins. |
4 | TRIP | I/O | Current limit setting pin. Connect a resistor to ground to set the current limit trip point. See Section 6.3.7 for detailed OCP setting. |
5 | EN | I | Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating the EN pin is not recommended. |
6 | FB | I | Output feedback input. A resistor divider from the VOUT to AGND (tapped to FB pin) sets the output voltage. |
7 | AGND | G | Analog ground pin, reference point for internal control circuits |
8 | SS/REFIN | I/O | Internal reference voltage can be overridden by an external voltage source on this pin for tracking application. Connecting a capacitor to AGND increases soft-start time. |
9 | PGOOD | O | Open-drain power-good status signal. A high voltage indicates the FB voltage has moved inside the specified limits. |
10 | BOOT | I/O | Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to SW node. |
12 | MODE | I | The MODE pin sets the forced continuous-conduction mode (FCCM) or skip-mode operation. It also selects the operating frequency. |
13 | VCC | I/O | Internal 3-V LDO output. An external bias with 3.3-V ±5% voltage can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal circuitry and gate driver. For the decoupling, suggest a 1-µF ceramic capacitor as close to VCC pin as possible. |