SLVSES4D September   2019  – June 2024 TPS54J060

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Enable and Internal LDO
      2. 6.3.2  Split Rail and External LDO
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Soft Start and Output-Voltage Tracking
      5. 6.3.5  Frequency and Operation Mode Selection
      6. 6.3.6  D-CAP3™ Control Mode
      7. 6.3.7  Current Sense and Positive Overcurrent Protection
      8. 6.3.8  Low-side FET Negative Current Limit
      9. 6.3.9  Power Good
      10. 6.3.10 Overvoltage and Undervoltage Protection
      11. 6.3.11 Out-Of-Bounds Operation (OOB)
      12. 6.3.12 Output Voltage Discharge
      13. 6.3.13 UVLO Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Pre-Bias Start-up
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 7.2.2.2  Choose the Output Inductor (L)
        3. 7.2.2.3  Set the Current Limit (TRIP)
        4. 7.2.2.4  Choose the Output Capacitors (COUT)
        5. 7.2.2.5  Choose the Input Capacitors (CIN)
        6. 7.2.2.6  Feedback Network (FB Pin)
        7. 7.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 7.2.2.8  EN Pin Resistor Divider
        9. 7.2.2.9  VCC Bypass Capacitor
        10. 7.2.2.10 BOOT Capacitor
        11. 7.2.2.11 Series BOOT Resistor and RC Snubber
        12. 7.2.2.12 PGOOD Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Ordering Information

7.2.2.4 Choose the Output Capacitors (COUT)

There are three considerations for selecting the value of the output capacitor:

  1. Stability
  2. Steady state output voltage ripple
  3. Regulator transient response to a change load current
First, the minimum output capacitance must be calculated based on these three requirements. Equation 16 calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW to meet stability requirements. This requirement helps to keep the LC double pole close to the internal zero. See Table 6-2 for the location of the internal zero. Equation 17 calculates the minimum capacitance to meet the steady state output voltage ripple requirement of 10 mV. This calculation is for CCM operation and does not include the portion of the output voltage ripple caused by the ESR or ESL of the output capacitors.

Equation 16. TPS54J060
Equation 17. TPS54J060

Equation 18 and Equation 19 calculate the minimum capacitance to meet the transient response requirement of 18 mV with a 3-A step. These equations calculate the necessary output capacitance to hold the output voltage steady while the inductor current ramps up or ramps down after a load step.

Equation 18. TPS54J060
Equation 19. TPS54J060

The output capacitance needed to meet the overshoot requirement is the highest value so this sets the required minimum output capacitance for this example. Stability requirements can also limit the maximum output capacitance and Equation 20 calculates the recommended maximum output capacitance. This calculation keeps the LC double pole above 1/100th the fSW. It can be possible to use more output capacitance but the stability must be checked through a bode plot or transient response measurement. The selected output capacitance is 6x 47-µF 0805 6.3-V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias effects. The selected capacitors derate to 60% the nominal value giving an effective total capacitance of 169 µF. This effective capacitance meets the minimum and maximum requirements.

Equation 20. TPS54J060

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If using non-ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 21 to meet the ripple requirement and Equation 22 to meet the transient requirement. For more accurate calculations or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient requirements can be met.

Equation 21. TPS54J060
Equation 22. TPS54J060