SLVSFJ7D november   2021  – august 2023 TPSI3050-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristic Curves
    12. 6.12 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Transmission of the Enable State
      2. 8.3.2 Power Transmission
      3. 8.3.3 Gate Driver
      4. 8.3.4 Modes Overview
      5. 8.3.5 Three-Wire Mode
      6. 8.3.6 Two-Wire Mode
      7. 8.3.7 VDDP, VDDH, and VDDM Undervoltage Lockout (UVLO)
      8. 8.3.8 Power Supply and EN Sequencing
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Two-Wire or Three-Wire Mode Selection
        2. 9.2.2.2 Standard Enable, One-Shot Enable
        3. 9.2.2.3 CDIV1, CDIV2 Capacitance
        4. 9.2.2.4 RPXFR Selection
        5. 9.2.2.5 CVDDP Capacitance
        6. 9.2.2.6 Gate Driver Output Resistor
        7. 9.2.2.7 Start-up Time and Recovery Time
        8. 9.2.2.8 Supplying Auxiliary Current, IAUX From VDDM
        9. 9.2.2.9 VDDM Ripple Voltage
      3. 9.2.3 Application Curves
      4. 9.2.4 Insulation Lifetime
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Related Links
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Two-Wire Mode

Figure 8-4 shows the basic setup required for two-wire mode operation, which requires the EN signal and VSSP ground signal. EN can be driven up to 48 V. No current limiting resistor is required on EN because the TPSI3050-Q1 limits the input current based on the values set by the RPXFR resistor (see Table 8-2). In this example, the TPSI3050-Q1 is being used to drive back-to-back MOSFETs in a common-source configuration. CVDDP provides the required decoupling capacitance for the VDDP supply rail of the device. CDIV1 and CDIV2 provide the required decoupling capacitance of the VDDH and VDDM supply rails that provide the peak current to drive the external MOSFETs.

Figure 8-5 shows the typical operation in two-wire mode configured for standard enable. The application drives EN to a logic high and the TPSI3050-Q1 begins its power-up sequence. During power up, the current provided by the EN pin, IEN, begins to charge up the external capacitance, CVDDP, and the voltage on VDDP begins to rise until it reaches VVDDP_H. After VDDP reaches its peak, VVDDP_H, the TPSI3050-Q1 transfers stored energy on CVDDP to the secondary side for a fixed time (3.3-μs typical) which begins to charge up the VDDH (and VDDM) secondary side rails thereby discharging the voltage on VDDP. In steady state, this results in an average voltage on VDDP, VVDDP_AVG. This cycle repeats until the VDDH (and VDDM) secondary side rails are fully charged. The time required to fully charge VDDH depends on several factors including the values of CVDDP, CDIV1, CDIV2, RPXFR, and the overall power transfer efficiency. After VDDH is fully charged, VDRV is asserted high and remains high while the EN pin remains at a logic high. When the application drives the EN pin to a logic low, the charge on VDDP begins to discharge. Prior to VDDP reaching its UVLO falling threshold, TPSI3050-Q1 signals information from the primary side to the secondary side to de-assert VDRV and drive it low. Because power is no longer being transferred, all rails begin to fully discharge.

GUID-20201201-CA0I-0WFV-MVVR-VXSGSJZPCDN8-low.svg Figure 8-4 Two-Wire Mode Simplified Schematic
GUID-20201201-CA0I-PW6V-SFGS-LLL7XS81R7ZL-low.svg Figure 8-5 Two-Wire Mode with Standard Enable (TPSI3050-Q1 Only)

In two-wire mode, power is supplied directly by the EN pin. When EN is asserted high, the TPSI3050-Q1 transfers power to the secondary side for a fixed time (3.3-μs nominal) while the time period varies. The period varies due to the hysteretic control of the power transfer that ensures the average current supplied through the EN pin is maintained. The amount of average current, and hence the amount of power transferred, is programmable by selecting one of seven appropriate resistor values, RPXFR, from the PXFR to VSSP pins. Higher settings of RPXFR increase IEN which increases the average power consumed from the EN pin and increases the amount of power transferred to the secondary side VDDH supply. Similarly, lower settings of RPXFR decrease IEN, which decreases the average power consumed from the EN pin and decreases the amount of power transferred to the secondary side.

Table 8-2 summarizes the two-wire mode power selection.

Table 8-2 Two-Wire Mode Power Selection
RPXFR (1)(2) IEN (Two-Wire Mode, Nominal) Description
7.32 kΩ 1.9 mA The device supports seven, fixed EN input current limit options selected by the corresponding RPXFR specified value. Higher current limit selections lead to increased power transfer and consumption. During power up, the EN input current limit is determined and remains fixed at that setting until VDDP power cycles.
9.09 kΩ 2.8 mA
11 kΩ 3.7 mA
12.7 kΩ 4.5 mA
14.7 kΩ 5.2 mA
16.5 kΩ 6.0 mA
20 kΩ 6.7 mA
Standard resistor (EIA E96), 1% tolerance, nominal value.
RPXFR ≥ 100 kΩ or RPXFR ≤ 1 kΩ sets the IEN to 1.9 mA.