SLVSFO5D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

GUID-F38E1E64-1827-4ECE-B252-80D7A96B43F5-low.gifFigure 6-1 YBH 4-Pin DSBGA Package
(TLV841S)
Top View
GUID-1396BF26-D158-41FF-8E60-D7B084F39B34-low.gifFigure 6-2 YBH 4-Pin DSBGA Package
(TLV841C)
Top View
GUID-283DD9B2-6FB5-4DC4-954D-871C79EEBC85-low.gif Figure 6-3 YBH 4-Pin DSBGA Package
(TLV841M)
Top View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
PIN NO. TLV841S TLV841C TLV841M
A1 RESET RESET RESET O Active-Low Output Reset Signal for TLV841xxxL: This pin is driven logic low when VDD and SENSE voltage falls below the negative voltage threshold (VIT-) or when the MR voltage falls below the logic low threshold. RESET remains logic low (asserted) until MR is above the logic high threshold or for the duration of the delay time period (tD) after VDD or SENSE voltage rises above VIT- + VHYS
A1 RESET RESET RESET O Active-High Output Reset Signal for TLV841xxxH: This pin is driven logic high when VDD or SENSE voltage falls below the negative voltage threshold (VIT-) or when the MR voltage falls below the logic low threshold. RESET remains logic high (asserted) until MR is above the logic high threshold or for the duration of the delay time period (tD) after VDD or SENSE voltage rises above VIT- + VHYS
A2 VDD VDD VDD I Input Supply Voltage: The VDD pin connects to the power supply to power the device. TLV841C and TLV841M monitor VDD voltage. TLV841S monitors SENSE only. Good analog design practice recommends placing a minimum 0.1 µF ceramic capacitor as near as possible to the VDD pin.
B1 SENSE _ _ I SENSE pin: This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the negative threshold voltage VIT-, reset asserts. When the voltage on SENSE rises above the positive threshold voltage (VIT- + VHYS), reset deasserts. For noisy applications, placing a 10 nF to 100 nF ceramic capacitor close to this pin may be needed for optimum performance.
B1 _ CT _ I Capacitor Time Delay Pin: The CT pin offers a user-programmable reset deassert delay time. Connect an external capacitor on this pin to adjust time delay. When not in use leave pin floating for the smallest fixed time delay.
B1 _ _ MR I Manual Reset: Pull this pin to a logic low to assert a reset signal in the RESET output pin (RESET signal for DL and PL option). After MR pin is left floating or pulls to logic high, the RESET output deasserts to the nominal state after the reset delay time (tD)expires. If unused, the pin can be left floating or connected to VDD.
B2 GND GND GND _ Ground