SLVSFQ0B October   2020  – June 2024 TPS54J061

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Enable and Internal LDO
      2. 6.3.2  Split Rail and External LDO
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Soft Start and Output-Voltage Tracking
      5. 6.3.5  Frequency and Operation Mode Selection
      6. 6.3.6  D-CAP3™ Control Mode
      7. 6.3.7  Current Sense and Positive Overcurrent Protection
      8. 6.3.8  Low-side FET Negative Current Limit
      9. 6.3.9  Power Good
      10. 6.3.10 Overvoltage and Undervoltage Protection
      11. 6.3.11 Out-Of-Bounds Operation (OOB)
      12. 6.3.12 Output Voltage Discharge
      13. 6.3.13 UVLO Protection
      14. 6.3.14 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
      3. 6.4.3 Pre-Bias Start-up
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 7.2.2.2  Choose the Output Inductor (L)
        3. 7.2.2.3  Set the Current Limit (TRIP)
        4. 7.2.2.4  Choose the Output Capacitors (COUT)
        5. 7.2.2.5  Choose the Input Capacitors (CIN)
        6. 7.2.2.6  Feedback Network (FB Pin)
        7. 7.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 7.2.2.8  EN Pin Resistor Divider
        9. 7.2.2.9  VCC Bypass Capacitor
        10. 7.2.2.10 BOOT Capacitor
        11. 7.2.2.11 Series BOOT Resistor and RC Snubber
        12. 7.2.2.12 PGOOD Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Support Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Trademarks
    5. 8.5 Glossary
    6. 8.6 Electrostatic Discharge Caution
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Ordering Information

4 Pin Configuration and Functions

TPS54J061 14-Pin VQFN-HR, RPG Package (Top View)Figure 4-1 14-Pin VQFN-HR, RPG Package
(Top View)
TPS54J061 14-Pin VQFN-HR, RPG Package (Bottom View)Figure 4-2 14-Pin VQFN-HR, RPG Package (Bottom View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1, 14 PGND G Power ground of internal low-side MOSFET
2., 11 SW O Output switching terminal of the power converter. Connect this pin to the output inductor.
3 VIN I Power-supply input pins for both integrated power MOSFET pair and the internal regulator. Place the decoupling input capacitors as close as possible to VIN pins.
4 TRIP I/O Current limit setting pin. Connect a resistor to ground to set the current limit trip point. See Section 6.3.7 for detailed OCP setting.
5 EN I Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating the EN pin is not recommended.
6 FB I Output feedback input. A resistor divider from the VOUT to AGND (tapped to FB pin) sets the output voltage.
7 AGND G Analog ground pin, reference point for internal control circuits
8 SS/REFIN I/O Internal reference voltage can be overridden by an external voltage source on this pin for tracking application. Connecting a capacitor to AGND increases soft-start time.
9 PGOOD O Open-drain power-good status signal. A high voltage indicates the FB voltage has moved inside the specified limits.
10 BOOT I/O Supply rail for the high-side gate driver (boost terminal). Connect the bootstrap capacitor from this pin to SW node.
12 MODE I The MODE pin sets the forced continuous-conduction mode (FCCM) or skip-mode operation. It also selects the operating frequency.
13 VCC I/O Internal 3-V LDO output. An external bias with 3.3-V ±5% voltage can be connected to this pin to save the power losses on the internal LDO. The voltage source on this pin powers both the internal circuitry and gate driver. For the decoupling, a 1-µF ceramic capacitor as close to VCC pin as possible is suggested.
(1) I = Input, O = Output, P = Supply, G = Ground