SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

9.4.1 Layout Guidelines

Component placement:

Decoupling capacitors for the primary side VDD supply must be placed as close as possible to the device pins.

EMI considerations:

The TPSI2140-Q1 employs spread spectrum modulation (SSM) and in some systems, no additional system design considerations are required to meet the EMI performance needs.

However, the system designer may choose to take additional measures to minimize EMI depending on the system requirements and safety preferences of the system designer. The measures listed below reduce emissions by providing a capacitive return path from the secondary side to the primary side or by increasing the common mode loop impedance with an inductive component on the primary side.

  • Capacitive Return Paths:
    • An interlayer stitching capacitance in the range of 10-20 pF can be implemented on the PCB. This zero-cost implementation is typically preferred as it also serves the purpose of thermal performance improvement if placed directly underneath the TPSI2140-Q1. Please see the Layout Example for more details.
    • Most system designs already employ discrete Y capacitors or contain an amount of parasitic Y capacitance between the high voltage and low voltage domains. If this Y capacitance is located on the same board as the TPSI2140-Q1, they will act as a capacitive return path.
    • Discrete high voltage capacitors could also be placed between the GND pin and the S1 or S2 terminals.
  • Inductive Components:
    • A pair of ferrite beads or a common mode choke with a high frequency impedance in the range of 10 kΩ may be placed in series with the system VDD pin and GND pin supply on the primary side of the TPSI2140-Q1.

High-voltage considerations:

The creepage from the primary side to the secondary side and from the creepage from the S1 pin to S2 pin of the TPSI2140-Q1 should be maintained according to system requirements. It is most likely that the system designer will avoid any top layer PCB routing underneath the body of the package or between the S1 and S2 pins.

Thermal considerations:

If the system designer plans to use the TPSI2140-Q1 in avalanche mode, it is important for the PCB layout to be designed with thermal performance in mind. Proper PCB layout can help dissipate heat from the device to the PCB and keep the junction temperature (TJ) under the absolute maximum rating. Floating inner layer planes or the planes used to implement a stitch capacitor can be drawn beneath the secondary side pins or directly beneath the TPSI2140-Q1 for improved heat dissipation. An example of this can be seen in the Layout Example.