SLVSFR3B april   2022  – june 2023 TPSI2140-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Avalanche Robustness
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Dielectric Withstand Testing (HiPot)
      2. 9.2.2 Design Requirements
      3. 9.2.3 Design Procedure - Chassis Ground Reference
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Dielectric Withstand Testing (HiPot)

The TPSI2140-Q1 is specifically designed to support dielectric withstand testing. In a high voltage system, a dielectric withstand test (HiPot) may be administered during the characterization, production or maintenance of the system to validate the reliability of the insulation barriers and galvanically isolated domains it contains. These withstand voltage tests intentionally stress the components spanning these domains and put them in an overvoltage condition. MOSFETs that are placed under these overvoltage conditions will enter avalanche mode and begin conducting current at a high voltage, dissipating high power and heating up. The design and qualification of the TPSI2140-Q1 was completed with this state in mind and supports up to 2 mA IAVA for 5 seconds intervals and 1 mA IAVA for 60 second intervals.

The dielectric withstand test voltage (VHiPot), the TPSI2140-Q1's avalanche voltage (VAVA), and the resistance (R) in series with the TPSI2140-Q1 should limit the avalanche current (IAVA) to the corresponding current limit depending on the test duration. In addition, the PCB design should follow the recommendations in the Layout Guidelines section to ensure adequate thermal performance to keep the junction temperature (TJ) below the absolute maximum rating of the TPSI2140-Q1.

GUID-20230524-SS0I-RQCV-FL5Q-F7PFDS9DNWBN-low.svg Figure 9-10 Dielectric Withstand Test (HiPot) - Simplified Schematic