SLVSFS6C May   2021  – March 2023 TPS629210-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Thermal Information - DYC Package
    6. 7.6 Electrical Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
      2. 8.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4 Smart Enable with Precise Threshold
      5. 8.3.5 Power Good (PG)
      6. 8.3.6 Output Discharge Function
      7. 8.3.7 Undervoltage Lockout (UVLO)
      8. 8.3.8 Current Limit and Short Circuit Protection
      9. 8.3.9 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM/PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Powering Multiple Loads
      2. 9.3.2 Inverting Buck-Boost (IBB)
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

9.5.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

The following are basic approaches for enhancing thermal performance:

  • Improving the power dissipation capability of the PCB design (for example, increasing copper thickness, thermal vias, number of layers)
  • Introducing airflow in the system

For more details on how to use the thermal parameters, see the Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs Application Note and Semiconductor and IC Package Thermal Metrics Application Note.

The TPS629210-Q1 is designed for a maximum operating junction temperature (TJ) of 150°C. Therefore, the maximum output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To get an improved thermal behavior, TI recommends to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance. Additionally, the DYC package option (see GUID-4BBB4DF5-86F7-4656-AC2B-BB1CDCF34D75.html#FIG_JCX_XKY_4WB) with extended leads can also be used to further reduce the thermal resistance of a design.

If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.