SLVSFU7B July   2022  – April 2024 TPS929240-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Bias and Power
        1. 6.3.1.1 Power Bias (VBAT)
        2. 6.3.1.2 5V Low-Drop-Out Linear Regulator (VLDO)
        3. 6.3.1.3 Undervoltage Lockout (UVLO) and Power-On-Reset (POR)
        4. 6.3.1.4 Power Supply (SUPPLY)
        5. 6.3.1.5 Programmable Low Supply Warning
      2. 6.3.2 Constant Current Output
        1. 6.3.2.1 Reference Current with External Resistor (REF)
        2. 6.3.2.2 64-Step Programmable High-Side Constant-Current Output
      3. 6.3.3 PWM Dimming
        1. 6.3.3.1 PWM Generator
        2. 6.3.3.2 PWM Dimming Frequency
        3. 6.3.3.3 Blank Time
        4. 6.3.3.4 Phase Shift PWM Dimming
        5. 6.3.3.5 Linear Brightness Control
        6. 6.3.3.6 Exponential Brightness Control
      4. 6.3.4 FAIL-SAFE State Operation
      5. 6.3.5 On-Chip, 8-Bit, Analog-to-Digital Converter (ADC)
        1. 6.3.5.1 Minimum On Time for ADC Measurement
        2. 6.3.5.2 ADC Auto Scan
        3. 6.3.5.3 ADC Error
      6. 6.3.6 Diagnostic and Protection in NORMAL State
        1. 6.3.6.1  VBAT Undervoltage Lockout Diagnostics in NORMAL state
        2. 6.3.6.2  Low-Supply Warning Diagnostics in NORMAL State
        3. 6.3.6.3  Supply Undervoltage Diagnostics in NORMAL State
        4. 6.3.6.4  Reference Diagnostics in NORMAL state
        5. 6.3.6.5  Pre-Thermal Warning in NORMAL state
        6. 6.3.6.6  Overtemperature Protection in NORMAL state
        7. 6.3.6.7  Overtemperature Shutdown in NORMAL state
        8. 6.3.6.8  LED Open-Circuit Diagnostics in NORMAL state
        9. 6.3.6.9  LED Short-Circuit Diagnostics in NORMAL state
        10. 6.3.6.10 Single-LED Short-Circuit Detection in NORMAL state
        11. 6.3.6.11 EEPROM CRC Error in NORMAL state
        12. 6.3.6.12 Communication Loss Diagnostic in NORMAL State
        13. 6.3.6.13 Fault Masking in NORMAL state
        14.       53
      7. 6.3.7 Diagnostic and Protection in FAIL-SAFE states
        1. 6.3.7.1  Supply Undervoltage Lockout Diagnostics in FAIL-SAFE states
        2. 6.3.7.2  Low-Supply Warning Diagnostics in FAIL-SAFE states
        3. 6.3.7.3  Supply Undervoltage Diagnostics in FAIL-SAFE State
        4. 6.3.7.4  Reference Diagnostics in FAIL-SAFE states
        5. 6.3.7.5  Pre-Thermal Warning in FAIL-SAFE state
        6. 6.3.7.6  Overtemperature Protection in FAIL-SAFE state
        7. 6.3.7.7  Overtemperature Shutdown in FAIL-SAFE state
        8. 6.3.7.8  LED Open-Circuit Diagnostics in FAIL-SAFE state
        9. 6.3.7.9  LED Short-Circuit Diagnostics in FAIL-SAFE state
        10. 6.3.7.10 Single-LED Short-Circuit Detection in FAIL-SAFE state
        11. 6.3.7.11 EEPROM CRC Error in FAIL-SAFE State
        12. 6.3.7.12 Fault Masking in FAIL-SAFE state
        13.       Diagnostics Table in FAIL-SAFE State
      8. 6.3.8 OFAF Setup In FAIL-SAFE state
      9. 6.3.9 ERR Output
    4. 6.4 Device Functional Modes
      1. 6.4.1 POR State
      2. 6.4.2 INITIALIZATION state
      3. 6.4.3 NORMAL state
      4. 6.4.4 FAIL-SAFE state
      5. 6.4.5 PROGRAM state
    5. 6.5 Programming
      1. 6.5.1 FlexWire Protocol
        1. 6.5.1.1 Protocol Overview
        2. 6.5.1.2 UART Interface Address Setting
        3. 6.5.1.3 Status Response
        4. 6.5.1.4 Synchronization Byte
        5. 6.5.1.5 Device Address Byte
        6. 6.5.1.6 Register Address Byte
        7. 6.5.1.7 Data Frame
        8. 6.5.1.8 CRC Frame
        9. 6.5.1.9 Burst Mode
      2. 6.5.2 Registers Lock
      3. 6.5.3 Register Default Data
      4. 6.5.4 EEPROM Programming
        1. 6.5.4.1 Chip Selection by Pulling REF Pin High
        2. 6.5.4.2 Chip Selection by ADDR Pins Configuration
        3. 6.5.4.3 EEPROM Register Access and Burn
        4. 6.5.4.4 EEPROM PROGRAM State Exit
    6. 6.6 Register Maps
      1. 6.6.1 BRT Registers
      2. 6.6.2 IOUT Registers
      3. 6.6.3 CONF Registers
      4. 6.6.4 CTRL Registers
      5. 6.6.5 FLAG Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Smart Rear Lamp with Distributed LED Drivers
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 150°C, V(VBAT) = 4.5-40 V, V(SUPPLY) = 4-36 V, for digital outputs, C(LOAD) = 20 pF, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BIAS
V(VBAT) Operating input voltage 4.5 12 40 V
IQ(VBAT) Quiescent current, all-channels-off, VBAT pin V(VBAT) = 12V, R(REF) = 8.45kΩ, REFRANGE = 11b, all-output OFF 1.6 2.0 mA
Quiescent current, all-channels-on, VBAT pin V(VBAT) = 12V, R(REF) = 8.45kΩ, REFRANGE = 11b, PWMOUTXn = 0, all-output ON 2.8 4.0 mA
IQ(SUPPLY) Quiescent current, all-channels-off, SUPPLY pin V(VBAT) = 12V, V(SUPPLY) = 12V, R(REF) = 8.45kΩ, REFRANGE = 11b, all-output OFF 4.9 10 µA
Quiescent current, all-channels-on, SUPPLY pin V(VBAT) = 12V, V(SUPPLY) = 12V, R(REF) = 8.45kΩ, REFRANGE = 11b, PWMOUTXn = 0, all-output ON 5.2 8.0 mA
IFAULT(VBAT) Quiescent current, fail-safe state fault mode, VBAT pin V(VBAT) = 12V, V(SUPPLY) = 12V, fail-safe state, all-output OFF, ERR = LOW 1.3 2.0 mA
IFAULT(SUPPLY) Quiescent current, fail-safe state fault mode, SUPPLY pin V(VBAT) = 12V, V(SUPPLY) = 12V, fail-safe state, all-output OFF, ERR = LOW 5 10 µA
ILKG(SUPPLY) Supply leakage current V(SUPPLY) = 36V, V(VBAT) = 0V 0.08 5 µA
V(POR_rising) Power-on-reset rising threshold 4 4.2 4.4 V
V(POR_falling) Power-on-reset falling threshold 3.8 4 4.2 V
V(LDO) LDO output voltage V(VBAT) > 5.6V, I(LDO) = 80mA 4.75 5 5.25 V
I(LDO) LDO output current capability 80 mA
I(LDO_LIMIT) LDO output current limit 110 mA
V(LDO_DROP) LDO maximum dropout voltage I(LDO) = 80mA 0.5 0.9 V
V(LDO_DROP) LDO maximum dropout voltage I(LDO) = 50mA 0.3 0.6 V
V(LDO_POR_rising) LDO power-on-reset rising threshold 2.75 3.00 3.25 V
V(LDO_POR_falling) LDO power-on-reset falling threshold 2.5 2.75 3 V
C(LDO) Supported LDO loading capacitance range 1 10 µF
f(OSC) Internal oscillator frequency -2.5% 32.15 +2.5% MHz
ERR
VIL(ERR) Input logic low voltage, ERR 1.045 1.1 1.155 V
VIH(ERR) Input logic high voltage, ERR 1.14 1.2 1.26 V
IPD(ERR) ERR pull-down current capability V(ERR) = 0.4V 3 5 9 mA
ILKG(ERR) ERR leakage current 0.02 1 µA
FLEXWIRE INTERFACE
VIL(RX) Input logic low voltage, RX 0.7 V
VIH(RX) Input logic high voltage, RX 2 V
VOL(TX) Low-level output voltage, TX Isink = 5mA, 0 0.04 0.3 V
VOH(TX) High-level output voltage, TX Isource = 5mA, Vpull-up = 5V 4.7 4.9 5.0 V
Ilkg TX, RX –1 1 µA
ADDRESS, FS
VIL(ADDR) Input logic low voltage, ADDR2, ADDR1, ADDR0 0.7 V
VIH(ADDR) Input logic high voltage, ADDR2, ADDR1, ADDR0 2 V
VIL(IO) Input logic low voltage FS1, FS0 1.045 1.1 1.155 V
VIH(IO) Input logic high voltage, FS1, FS0 1.14 1.2 1.26 V
RPD(ADDR) Internal pull down resistance, ADDR2, ADDR1, ADDR0 200 240 300 kΩ
ADC
DNL Differential nonlinearity –1(1) 1(1) LSB
INL Integral nonlinearity –2(1) 2(1) LSB
OUTPUT DRIVERS
f(PWM_200) 200Hz selection 200 Hz
f(PWM_1000) 1kHz selection 1000 Hz
ΔI(OUT_d2d) Device-to-device accuracy ΔI(OUT_d2d) = 1- Iavg(OUT) / Iideal(OUT) R(REF) = 8.45kOhm, REFRANGE = 11b, DC = 63 –5 0 5 %
R(REF) = 8.45kΩ, REFRANGE = 10b, DC = 63 –5 0 5
R(REF) = 8.45kΩ, REFRANGE = 01b, DC = 63 –5 0 5
R(REF) = 8.45kΩ, REFRANGE = 00b, DC = 63 –5 0 5
ΔI(OUT_c2c) Channel-to-channel accuracy ΔI(OUT_c2c) = 1- I(OUTx) / Iavg(OUT) R(REF) = 8.45kΩ, REFRANGE = 11b, DC = 63 –3 0 3 %
R(REF) = 8.45kΩ, REFRANGE = 10b, DC = 31 –3 0 3
R(REF) = 8.45kΩ, REFRANGE = 01b, DC = 15 –5 0 5
R(REF) = 31.6kΩ, REFRANGE = 01b, DC = 12 –7 0 7
I(OUT_100mA) R(REF) = 6.34kΩ, REFRANGE = 11b, DC = 63 100 mA
I(OUT_75mA) R(REF) = 8.45kΩ, REFRANGE = 11b, DC = 63 75 mA
I(OUT_50mA) R(REF) = 12.7kΩ, REFRANGE = 11b, DC = 63 50 mA
I(OUT_20mA) R(REF) = 31.6kΩ, REFRANGE = 11b, DC = 63 20 mA
I(OUT_1mA) R(REF) = 31.6kΩ, REFRANGE = 01b, DC = 12 1 mA
V(OUT_drop) Output dropout voltage R(REF) = 8.45kΩ, REFRANGE = 11b, DC = 38, I(OUTx) = 45mA 450 700 mV
R(REF) = 8.45kΩ, REFRANGE = 11b, DC = 63, I(OUTx) = 75mA 600 1000 mV
R(REF) = 6.34kΩ, REFRANGE = 11b, DC = 63, I(OUTx) = 100mA 750 1200 mV
R(REF) 1 50 kΩ
C(REF) 0 4.7 nF
V(REF) 1.228 1.235 1.242 V
K(REF_11) REFRANGE = 11b 512
K(REF_10) REFRANGE = 10b 256
K(REF_01) REFRANGE = 01b 128
K(REF_00) REFRANGE = 00b 64
I(REF_OPEN_th) 7 8.5 10 µA
I(REF_OPEN_th_hyst) 4 uA
V(REF_SHORT_th) 0.54 0.565 0.59 V
DIAGNOSTICS
V(SUPUV_th_rising) SUPPLY undervoltage rising threshold 2.73 2.875 3.02 V
V(SUPUV_th_falling) SUPPLY undervoltage falling threshold 2.49 2.625 2.76 V
V(SUPUV_th_hyst) SUPPLY undervoltage hysteresis 250 mV
V(SUPLOW_th_rising) SUPPLY low rising threshold, LOWSUPTH = 0 4.05 4.25 4.45 V
V(SUPLOW_th_falling) SUPPLY low falling threshold, LOWSUPTH = 0 3.8 4.0 4.2 V
V(SUPLOW_th_hyst) SUPPLY low hysteresis, LOWSUPTH = 0 250 mV
V(OPEN_th_rising) LED open rising threshold V(SUPPLY) - V(OUTx) 200 400 600 mV
V(OPEN_th_falling) LED open falling threshold V(SUPPLY) - V(OUTx) 300 500 700 mV
V(OPEN_th_hyst) 100 mV
V(SG_th_rising) Short-to-ground rising threshold 0.8 0.9 1 V
V(SG_th_falling) Short-to-ground falling threshold 1.1 1.2 1.3 V
V(SG_th_hyst) Short-to-ground hysteresis 0.3 V
V(SLS_th_rising) Single-LED short rising threshold, SLSTHx = 0 2.35 2.5 2.65 V
V(SLS_th_falling) Single-LED short falling threshold, SLSTHx = 0 2.65 2.85 3.05 V
V(SLS_th_hyst) Single-LED short hysteresis, SLSTHx = 0 275 mV
EEPROM
N(EEP) Number of programming cycles V(VBAT) = 12V 1000
TEMPERATURE
T(PRETSD) Pre-thermal warning threshold 135 oC
T(PRETSD_HYS) Pre-thermal warning hysteresis 5 oC
T(TSD1) Over-temperature
protection threshold		 160 175 190 oC
T(TSD2) Over-temperature
shutdown threshold		 185 oC
T(TSD1_HYS) Over-temperature
protection hysteresis		 15 oC
T(TSD2_HYS) Over-temperature
shutdown hysteresis		 15 oC
(1) Specified by design only