SLVSG41 January   2022 TPS7H4003-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjust UVLO
      7. 7.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 7.3.7.1 Internal Oscillator Mode
        2. 7.3.7.2 External Synchronization Mode
        3. 7.3.7.3 Primary-Secondary Operation Mode
      8. 7.3.8  Soft-Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Sequencing
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Turn-On Behavior
      15. 7.3.15 Slope Compensation
        1. 7.3.15.1 Slope Compensation Requirements
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Output Schottky Diode
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Soft-Start Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 8.2.2.8 Output Voltage Feedback Resistor Selection
          1. 8.2.2.8.1 Minimum Output Voltage
        9. 8.2.2.9 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.16 Small Signal Model for Frequency Compensation

The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency compensation circuits shown in Figure 7-10. In Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.

The following design guidelines are provided for advanced users who prefer to compensate using the general method.

GUID-F7945B54-EAD3-4D47-B3FD-14C346968A31-low.gifFigure 7-10 Types of Frequency Compensation

The general design guidelines for device loop compensation are as follows:

  1. Determine the crossover frequency fco. A good starting point is one-tenth of the switching frequency, ƒSW.
  2. R3 can be determined by:
    Equation 19. GUID-E2955B2F-8F05-48C6-89EB-9F40D39ABB0B-low.gif

    where gmea is the transconductance of the error amplifier (1800 μS), gmps is the transconductance of the power stage (40 S) and VREF is the reference voltage (0.605 V).

  3. Place a compensation zero at the dominant pole calculated in Equation 20 using C1 and R3.
    C1 can be determined by Equation 21.
    Equation 20. GUID-5F910379-8532-46D4-B2C8-4565FC0E0449-low.gif
    Equation 21. GUID-7AE24B5F-146E-4143-AB0D-EA6126715FE7-low.gif
  4. C2 is optional. It can be used to cancel the zero from the equivalent series resistance (ESR) of the output capacitor COUT.
    Equation 22. GUID-90C7759A-CC7A-442B-8910-2F4BC4C3A5D2-low.gif