SLVSG41 January   2022 TPS7H4003-SEP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and Power VIN Pins (VIN and PVIN)
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Safe Start-Up Into Prebiased Outputs
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjust UVLO
      7. 7.3.7  Adjustable Switching Frequency and Synchronization (SYNC)
        1. 7.3.7.1 Internal Oscillator Mode
        2. 7.3.7.2 External Synchronization Mode
        3. 7.3.7.3 Primary-Secondary Operation Mode
      8. 7.3.8  Soft-Start (SS/TR)
      9. 7.3.9  Power Good (PWRGD)
      10. 7.3.10 Sequencing
      11. 7.3.11 Output Overvoltage Protection (OVP)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.12.2 Low-Side MOSFET Overcurrent Protection
      13. 7.3.13 Thermal Shutdown
      14. 7.3.14 Turn-On Behavior
      15. 7.3.15 Slope Compensation
        1. 7.3.15.1 Slope Compensation Requirements
      16. 7.3.16 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed-Frequency PWM Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Operating Frequency
        2. 8.2.2.2 Output Inductor Selection
        3. 8.2.2.3 Output Capacitor Selection
        4. 8.2.2.4 Output Schottky Diode
        5. 8.2.2.5 Input Capacitor Selection
        6. 8.2.2.6 Soft-Start Capacitor Selection
        7. 8.2.2.7 Undervoltage Lockout (UVLO) Set Point
        8. 8.2.2.8 Output Voltage Feedback Resistor Selection
          1. 8.2.2.8.1 Minimum Output Voltage
        9. 8.2.2.9 Compensation Component Selection
      3. 8.2.3 Parallel Operation
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.3.15.1 Slope Compensation Requirements

All the design parameters are relevant when configuring the slope compensation. The first requirement is that the inductor peak current ILpeak must be less than the compensated maximum high side FET current, ILmax as shown in Equation 12.

Equation 12. GUID-95F8C1C3-F550-4FBB-865E-094CD3AD8336-low.gif

ILpeak can be calculated as shown in Equation 13, where KL relates Iripple the inductor ripple current, to IO the output current, as shown in Equation 14.

Equation 13. GUID-8EC7957D-A472-40F9-818D-D1A51E114A19-low.gif
Equation 14. GUID-755BAA49-63CD-454B-83BF-7E9F7D039944-low.gif

ILmax is defined as the difference between the high side current limit specified in the Electrical Characteristics, and the change in current due to the ramp, ISC as shown in Equation 15. ISC can be calculated using Equation 16, where tON is the on time for the high side FET. tON depends on the switching frequency and is related to the duty cycle as shown in Equation 17.

Equation 15. GUID-78E47023-0024-49E8-A35E-F8FA33A2027F-low.gif
Equation 16. GUID-18FEA627-C255-4A74-B751-916425492626-low.gif
Equation 17. GUID-A2A4CDDA-BCD3-432D-8F59-7F07D8DAF495-low.gif

The last requirement related to the slope compensation is related to the maximum value for KL depending on the SC value selected so that the desired IO can be supported. In other words, the maximum value for KL such that ILpeak is less than ILmax. By substituting Equation 16 and Equation 17 into the combinations of Equation 13 and Equation 15, the equation for the maximum value for KL can be derived as shown in Equation 18.

Equation 18. GUID-AFE702D4-81BD-41A0-A237-D2FE71021E24-low.gif