SLVSGC1B December   2021  – August 2024 TPS63901

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Trapezoidal Current Control
      2. 6.3.2 Device Enable and Disable
      3. 6.3.3 Soft Start
      4. 6.3.4 Input Current Limit
      5. 6.3.5 Dynamic Voltage Scaling
      6. 6.3.6 Device Configuration (Resistor-to-Digital Interface)
      7. 6.3.7 SEL Pin
      8. 6.3.8 Short-Circuit Protection
        1. 6.3.8.1 Current Limit Setting = 'Unlimited'
        2. 6.3.8.2 Current Limit Setting = 1 mA to 100 mA
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Inductor Selection
        2. 7.2.2.2 Output Capacitor Selection
        3. 7.2.2.3 Input Capacitor Selection
        4. 7.2.2.4 Setting The Output Voltage
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C, VI = 3.0 V, VO = 2.5 V . Typical values are at TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current into VIN V(EN) = 3 V, no load, not switching,
"unlimited" current setting; TJ = –40°C to 85°C		 0.075  1 µA
ISD Shutdown current into VIN V(EN) = 0 V ; TJ = –40°C to 85°C 60 nA
VIT+(UVLO) Positive-going UVLO threshold voltage 1.73  1.75 1.77 V
Vhys(UVLO) UVLO threshold voltage hysteresis 90 100 110 mV
VIT+(POR) Positive-going POR threshold voltage  1.37 1.74 V
I/O SIGNALS
VIH High-level input voltage (EN, SEL) 1.2 V
VIL Low-level input voltage (EN, SEL) 0.4 V
Input current (EN, SEL) V(EN), V(SEL) = 1.8 V or 0 V ±1 ±10 nA
POWER SWITCH
rDS(on) On-state resistance Q1 VI = 3 V, VO = 5 V,   test current = 1 A 140 mΩ
Q2 VI = 3 V, VO = 3 V,  test current = 1 A 95
Q3 VI = 3 V, VO = 3 V, test current = 1 A 95
Q4 VI = 5 V, VO = 3 V, test current = 1 A 140
CURRENT LIMIT
Peak current limit during start-up (Q1) VI = 3.6 V,
unlimited current limit setting		 0.35
 0.83 A
Peak current limit (Q1)   VI = 1.8 V, VO = 3.6 V,
unlimited current limit setting
 1.33 1.45  1.6
 A
VI = 3.6 V, VO = 3.3 V,
100-mA current limit setting		 0.15 0.29 
 		 0.51
Average input current limit TJ = –40°C to 85°C 1-mA setting 1 mA
2.5-mA setting 2.5
5-mA setting 5
10-mA settting 10
25-mA setting 25
50-mA setting 50
100-mA setting 100
OUTPUT
Output voltage DC accuracy IO = 1 mA, CO(eff) = 10 µF, L(eff) = 2.2 µH  ±1.5%
CONTROL
Internal reference resistor 33 kΩ
RCFG R2D setting #0 0 0.1 kΩ
R2D setting #1 –3% 0.511 +3%
R2D setting #2 –3% 1.15 +3%
R2D setting #3 –3% 1.87 +3%
R2D setting #4 –3% 2.74 +3%
R2D setting #5 –3% 3.83 +3%
R2D setting #6 –3% 5.11 +3%
R2D setting #7 –3% 6.49 +3%
R2D setting #8 –3% 8.25 +3%
R2D setting #9 –3% 10.5 +3%
R2D setting #10 –3% 13.3 +3%
R2D setting #11 –3% 16.2 +3%
R2D setting #12 –3% 20.5 +3%
R2D setting #13 –3% 24.9 +3%
R2D setting #14 –3% 30.1 +3%
R2D setting #15 –3% 36.5 +3%
PROTECTION FEATURES
Thermal shutdown threshold temperature 140 150 160 °C
Thermal shutdown hysteresis 15 20 25 °C
TIMING PARAMETERS
td(POR) POR signal delay after reaching POR threshold 3.8 ms
td(EN) Delay between a rising edge on the EN pin and the start of the output voltage ramp Supply voltage stable before EN pin goes high 1.5 ms
tw(SS) Soft-start step duration VO > 1.8 V 100 125 150 µs
td(SEL) Delay between a change in the state of the SEL pin and the first step change in the output voltage 30 40 µs
tw(DVS) Dynamic voltage scaling step duration 100 125 150 µs
td(RESTART) Restart delay after protection 10 11 ms