SLVSGH5B March 2023 – June 2024 ADC12DJ5200SE
PRODUCTION DATA
The ADC12DJ5200SE can also be used as a single-channel ADC where the sampling rate is equal to two times the clock frequency (fS = 2 × fCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by setting JMODE to the appropriate setting for the desired configuration as described in Table 6-24. INA or INB, can serve as the input to the ADC, however INA is recommended for highest performance. The analog input can be selected using SINGLE_INPUT (see the input mux control register). A calibration needs to be performance after switching the input mux for the changes to take effect.