SLVSGI0C September 2022 – June 2024 DRV8411
PRODUCTION DATA
The DRV8411 device supports a low power mode to reduce current consumption from the VM pin when the driver is not active. This mode is entered by setting nSLEEP = logic low and waiting for tSLEEP to elapse.
In sleep mode, the H-bridge, charge pump, internal regulator, and internal logic are disabled and the device draws minimal current from the supply pin (IVMQ). The device relies on a weak pulldown to ensure all of the internal MOSFETs remain disabled. If the device is powered up while the nSLEEP pin is low, it immediately enters sleep mode. After the nSLEEP pin is high for longer than the duration of tWAKE, the device becomes fully operational.
The following timing diagram shows an example of entering and leaving sleep mode.