SLVSGJ9 May   2024 DRV7308

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Absolute Maximum Ratings
  7. 6 ESD Ratings
  8. 7 Recommended Operating Conditions
  9. 8 Thermal Information
  10. 9 Electrical Characteristics
  11. 10Timing Diagrams
  12. 11Typical Characteristics
  13. 12Detailed Description
    1. 12.1 Overview
    2. 12.2 Functional Block Diagram
    3. 12.3 Feature Description
      1. 12.3.1 Output Stage
      2. 12.3.2 Input Control Logic
      3. 12.3.3 ENABLE (EN) Pin Function
      4. 12.3.4 Temperature Sensor Output (VTEMP)
      5. 12.3.5 Brake Function
      6. 12.3.6 Slew Rate Control (SR)
      7. 12.3.7 Dead Time
      8. 12.3.8 Current Limit Functionaity (ILIMIT)
      9. 12.3.9 Pin Diagrams
        1. 12.3.9.1 Four-Level Input Pin
        2. 12.3.9.2 Open-Drain Pin
        3. 12.3.9.3 Logic-Level Input Pin (Internal Pulldown)
    4. 12.4 Protections
      1. 12.4.1 GVDD Undervoltage Lockout
      2. 12.4.2 Bootstrap Undervoltage Lockout
      3. 12.4.3 Current Limit Protection
      4. 12.4.4 GaNFET Overcurrent Protection
      5. 12.4.5 Thermal Shutdown (OTS)
  14. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  15. 14Revision History
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Tape and Reel Information

1 Features

  • Three-phase PWM motor driver with integrated 650V enhancement mode GaNFETs
  • Up to 450V operating voltage
    • 650V absolute maximum voltage
  • High output current capability: 5A Peak current
  • Low conduction loss: Low on-state resistance per GaN FET: 205mΩ RDS(ON) at TA = 25°C
  • Low switching loss: Zero reverse recovery, low output capacitance, slew rate control
  • Low distortion: Ultra low propagation delay < 135ns, Ultra low adaptive dead time < 200ns
  • Integrated gate drives with slew rate control of phase node voltage
    • Slew rate options from 5V/ns to 40V/ns
  • 500ns minimum low side on time support with integrated fast bootstrap GaN rectifier
  • Low-side GaN FET open source pins to support 1- or 2- or 3-shunt current sensing
  • Supports up to 60kHz hard switching
  • Integrates a 11MHz, 15V/μs amplifier for single shunt current sensing
  • Supports 3.3V and 5V logic inputs
  • Integrated BRAKE functionality to turn on all low side GaN FETs together
  • Integrated temperature sensor
  • >1.6mm clearance between OUTx and OUTx, VM and OUTx and OUTx and PGND.
  • 2mm clearance between VM and PGND
  • Integrated protection features
    • GVDD and bootstrap under voltage lockout
    • Over current protection for each GaN FET
    • Over temperature protection
    • PWM input dead time
    • Current limit protection using integrated comparators for all three phases
    • Fault condition indication pin (HV_nFAULT)