The basic PCB board layout requires separation of sensitive signal and power paths. This checklist must be followed to get good performance for a well-designed board.

• Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the IN, OUT, and V_BUS capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high di/dt switching currents.
• Refer to Table 9-1 for suggested C_IN values. Place the input bypass capacitors, C_IN and C_{IN_HF}, as close to the IN and PGND pins as possible to minimize the loop area for input switching current in buck operation. The C_{IN_HF} capacitors must be as close as possible - see Figure 9-4. The IN and PGND pins transverse the package and it is highly recommended to split C_IN and C_{IN_HF} such that capacitors can be placed on either side.
• Place the output filter capacitors, C_OUT and C_{OUT_HF}, as close to the OUT and PGND pins as possible to minimize the loop area for output switching current in boost operation. Refer to Table 9-1 for suggested C_OUT and C_{OUT_HF} values.
• Place the current sense resistor and filter components. R_SNS, R_CSP, R_CSN, and C_FLT. Place the filter capacitor for the current sense signal as close to the IC CSP and CSN/BUS as possible. Use Kelvin connections between R_SNS through the CSP and CSN resistors and to the CSP and CSN/BUS pins to avoid creating offsets in the current sense amplifier. Avoid crossing noisy areas such as SW1 and SW2 nodes. The recommended values in Table 9-2 provide a good starting point but may require some fine adjustment to meet PPS current limit accuracy requirements. When deviating from recommended values, R_CSP must not be larger than 10 ohms. R_CSN must be 0 ohms. CFLT cannot be larger than 0.33 μF.
• Place C_BUS between the R_SNS and the USB Type-C connector. See Table 9-1 for suggested C_BUS values. .
• Place the C_IN, C_OUT, and C_BUS ground connections as close as possible to the IC with thick ground trace and/or planes on multiple layers.
• Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.
• Place the LDO_5V bypass capacitors, C_5V and C_{5V_HF} close to the IC pin, between the LDO_5V and PGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_5V supplies LDO_3V3 and LDO_1V5 as well as the low side buck and boost MOSFETs.
• Place the LDO_3V3 bypass capacitors, C_3V3 and C_{3V3_HF} close to the IC pin, between the LDO_3V3 and AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the analog IO circuits.
• Place the LDO_1V5 bypass capacitors, C_1V5 and C_{1V5_HF} close to the IC pin, between the LDO_1V5 and AGND pins. A 4.7 µF and 0.1 µF ceramic capacitors are typically used. LDO_3V3 supplies the Cortex M0 and digital circuits.
• Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins. For EMI mitigation, a series resistor R_BOOT1 may be added.
• Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins. For EMI mitigation, a series resistor R_BOOT2 may be added.
• Bypass the TVSP pin to PGND with a low ESR ceramic capacitor, C_TVSP located close to the IC. A 0.1 µF ceramic capacitor is typically used. R_{TVSP_DAMP} and C_{TVSP_DAMP} must be added in parallel close to C_TVSP. 10 Ω and 0.47 μF are recommended values.
• Use care to separate the power and signal paths so that no power or switching current flows through the AGND connections which can either corrupt the USB PD modem or GPIO signals. The PGND and AGND traces can be connected near the AGND pin.
• USB data lines, DP and DM must be differentially routed between the IC pins and USB connector. Impedance control is based on the PCB stack-up. 90 Ω differential is recommended. Route the DP and DM USB signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points on twisted pair lines; through-hole pins are not recommended. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn to reduce reflections on the signal traces by minimizing impedance discontinuities. Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, keep the length to less than 200 mm.
• CC lines must be routed with a 10-mil trace to ensure the needed current for supporting powered Type-C cables through VCONN. For more information on VCONN refer to the Type-C specifications. For the 330 pF CC capacitor GND pins use a 16-mil trace if possible.
• GPIO signals can be fanned out on the top or bottom layer using either a 8-mil or 10-mil trace.