SLVSGS7D July   2023  – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power-Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.17 Stacked Operation

The user can connect multiple devices in parallel in what is known as a "stack" to increase output current capability, to reduce device junction temperature or the output voltage ripple. For example, paralleling four 15-A devices can provide up to 60 A of current. More devices can be stacked, as long as the PCB layout maintains the integrity of the shared signals between the modules.

A stack comprises one primary device and one or more secondary devices. During initialization, each device monitors the SYNC_OUT pin to determine if it must operate as a primary device or a secondary device:

  • If there is a 47-kΩ resistor between the SYNC_OUT pin and ground, the device operates as a secondary device.
  • If the SYNC_OUT pin is high impedance, the device operates as a primary device.

Figure 7-22 shows the recommended interconnections in a stack of two TPSM8287Axx devices.


TPSM8287A06 TPSM8287A10 TPSM8287A12 TPSM8287A15 Two TPSM8287Axx Devices in a Stacked Configuration

Figure 7-22 Two TPSM8287Axx Devices in a Stacked Configuration

The key points to note are:

  • All the devices in the stack share a common enable signal, which must be pulled up with a resistance of at least 15 kΩ.
  • All secondary devices must connect a 47-kΩ resistor between the SYNC_OUT pin and ground.
  • All the devices in the stack share a common power-good signal, which must be pulled up with a resistor to a logic high level.
  • All the devices in the stack share a common compensation signal.
  • The remote sense pins (VOSNS and GOSNS) of each device must be connected (do not leave these pins floating).
  • The same device part number (with the same frequency and output current) must be used for all devices in the stack.
  • The primary device must be configured for forced-PWM operation (secondary devices are automatically configured for forced-PWM operation).
  • A stacked configuration can support synchronization to an external clock or spread-spectrum clocking.
  • Only the VSETx pins of the primary device are used to set the default output voltage. The VSETx pins of secondary devices are not used and must be connected to ground.
  • The SDA and SCL pins of secondary devices are not used and must be connected to ground.
  • A stacked configuration uses a daisy-chained clocking signal, in which each device switches with a phase offset of approximately 140° relative to the previous device in the daisy-chain. To daisy-chain the clocking signal, connect the SYNC_OUT pin of the primary device to the MODE/SYNC pin of the first secondary device. Connect the SYNC_OUT pin of the first secondary device to the MODE/SYNC pin of the second secondary device. Continue this connection scheme for all devices in the stack to daisy-chain them together.
  • Hiccup overcurrent protection must not be used in a stacked configuration.

  • For output voltages >=1.2V, reduce the maximum output current per phase by 1A to account for current balancing inaccuracy.

In a stacked configuration, the common enable signal also acts as a SYSTEM_READY signal (see Section 7.3.3). Each device in the stack can pull the EN pin low during device start-up or when a fault occurs. Thus, the stack is only enabled when all devices have completed the start-up sequence and are fault-free. A fault in any one device disables the whole stack for as long as the fault condition exists.

During start-up, the primary converter pulls the COMP pin low for as long as the enable signal (SYSTEM_READY) is low. When the enable signal goes high, the primary device actively controls the COMP pin and all converters in the stack follow the COMP voltage. During start-up, each device in the stack pulls the PG pin low while it initializes. When initialization is complete, each secondary device in the stack sets it PG pin to high impedance and the primary device alone controls the state of the PG signal. The PG pin goes high when the stack has completed the start-up ramp and the output voltage is within the power good window. The secondary converters in the stack detect the rising edge of the power-good signal and switch to FPWM operation. After the stack has successfully started up, the primary device controls the power-good signal in the normal way. In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal. For details refer to Table 7-7.

Functionality During Stacked Operation

Some device features are not available during stacked operation, or are only available in the primary converter. Table 7-6 summarizes the available functionality during stacked operation.

Table 7-6 Functionality During Stacked Operation
FunctionPrimary DeviceSecondary DeviceRemark
UVLOYesYesCommon enable signal
OVLOYesYesCommon enable signal
OCP – Current LimitYesYesIndividual device
OCP – Hiccup OCPNoNoDo not use during stacked operation
Thermal ShutdownYesYesCommon enable signal
Power Good (Window Comparator)YesNoPrimary device only
I2C InterfaceYesNoPrimary device only
DVSThrough I2CNoVoltage loop controlled by primary device only
SSCThrough I2CYes, through primary deviceDaisy-chained from primary device to secondary devices
SYNCYes

Yes, through primary device

Synchronization clock applied to primary device and daisy-chained from primary device to secondary devices

Precise EnableNoNoOnly binary enable
Output Discharge

Through I2C

Yes

Always enabled in secondary devices

Fault Handling During Stacked Operation

In a stacked configuration, there are some faults that only affect individual devices, and other faults that affect all devices. For example, if one device enters current limit, only that device is affected. But a thermal shutdown or undervoltage lockout event in one device disables all devices through the shared enable (SYSTEM_READY) signal. Table 7-7 summarizes the fault handling during stacked operation.

Table 7-7 Fault Handling During Stacked Operation
Fault ConditionDevice ResponseSystem Response
UVLOEnable signal pulled lowNew soft start
OVLO
Thermal Shutdown
Current LimitEnable signal remains highError amplifier clamped