SLVSGZ4A June   2023  – June 2024 TPS6521905

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6521905 default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.3.1 Buck1, Buck2, Buck3 Design Procedure

Input Capacitance - Buck1, Buck2, Buck3

Each of the Buck converters require an input capacitor on the corresponding PVIN_Bx pin. The capacitor value must be selected taking into account the voltage and temperature de-rating. Due to the nature of the switching converter, a low ESR ceramic capacitor is required for best input voltage filtering. The typical recommended capacitance is 4.7 uF, 10V capacitor. Higher input capacitance can be used if the PCB size allows larger footprint.

Output Capacitance - Buck1, Buck2, Buck3

Every Buck output requires a local output capacitor to form the capacitive part of the LC output filter. Ceramic capacitor with X7 temperature coefficient are recommended. Non-automotive applications can use X6 or lower based on the operating temperature. The Buck converters have multiple switching modes and bandwidth configuration that impact the output capacitor selection. The switching mode configuration (BUCK_FF_ENABLE) is a global register field that applies to the three Buck converters and must not be changed at any point. The bandwidth selection is an independent register field for each Buck converter. Refer to the Technical Reference Manual (TRM) for the specific orderable part number to identify the NVM configuration and the corresponding output capacitance requirements. Table 7-1 shows the required minimum and maximum capacitance (after derating) for each switching mode and bandwidth configuration. DC bias voltage characteristics of ceramic capacitors, tolerance, aging and temperature effects must be considered. ESR must be 10 mΩ or lower.

Table 7-1 Buck output capacitance
Switching Mode Selection Bandwidth Selection Spec parameter Capacitance
Register Field:

BUCK_FF_ENABLE

 Register fields:

BUCK1_BW_SEL, BUCK2_BW_SEL, BUCK3_BW_SEL

 Min Max

(Includes local + point of load)
Quasi-fixed frequency

(auto-PFM or forced-PWM)

 Low Bandwidth COUT 10 uF 75 uF
High Bandwidth COUT_HIGH_BW 30 uF 220 uF

Inductor Selection - Buck1, Buck2, Buck3

Internal parameters for the buck converters are optimized for 0.47uH inductor. DCR must be 50 mΩ or lower. Ensure that the selected inductor is rated to support saturation current of at least 7.4A for Buck1 and 5.4A for Buck2/Buck3.