SLVSH00 November   2024 TPD4S480

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—IEC Specification
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      4. 6.3.4 EPR Adapter
        1. 6.3.4.1 VBUS Divider
        2. 6.3.4.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 EPR Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 EPR Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     52

4 Pin Configuration and Functions

TPD4S480 RUK Package20-Pin QFN Figure 4-1 RUK Package20-Pin QFN
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
12 CC1 I/O System side of the CC1 OVP FET. Connect to either CC pin of the CC/PD controller.
11 CC2 I/O System side of the CC2 OVP FET. Connect to either CC pin of the CC/PD controller.
4 C_CC1 I/O Connector side of the CC1 OVP FET. Connect to either CC pin of the USB Type-C connector.
5 C_CC2 I/O Connector side of the CC2 OVP FET. Connect to either CC pin of the USB Type-C connector.
1 C_SBU1 I/O Connector side of the SBU1 OVP FET. Connect to either SBU pin of the USB Type-C connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to protect the USB2.0 pins instead of the SBU pins.
2 C_SBU2 I/O Connector side of the SBU2 OVP FET. Connect to either SBU pin of the USB Type-C connector. Alternatively, connect to either USB2.0 pin of the USB Type-C connector to protect the USB2.0 pins instead of the SBU pins.
15 SBU1 I/O System side of the SBU1 OVP FET. Connect to either SBU pin of the SBU MUX. Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the USB2.0 pins instead of protecting the SBU pins.
14 SBU2 I/O System side of the SBU2 OVP FET. Connect to either SBU pin of the SBU MUX. Alternatively, connect to either USB2.0 pin of the USB2.0 Phy when protecting the USB2.0 pins instead of protecting the SBU pins.
7 RPD_G1 I/O Short to C_CC1 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND.
6 RPD_G2 I/O Short to C_CC2 if dead battery resistors are needed. If dead battery resistors are not needed, short pin to GND.
9 FLT O Open drain for fault reporting.
8, 13, 18 GND GND Ground
3 VBIAS P Pin for ESD support capacitor. Place a 0.1-µF capacitor on this pin to ground.
10 VPWR P 2.7V to 4.5V power supply.
20 VBUS I Input for EPR VBUS divider. Tie to USB-C receptacle VBUS pins.
19 VBUS_LV O Output of EPR VBUS divider. When EPR_EN is asserted, VBUS_LV is divided down voltage from VBUS. When EPR_EN is de-asserted VBUS_LV is equal to VBUS.
16 EPR_EN I EPR mode enable input. When asserted EPR_BLK_G is disabled and VBUS_LV is divided VBUS.
17 EPR_BLK_G O Gate driver output to optional VBUS blocking FET. FET is enabled when in SPR mode and disabled in EPR mode.
- Thermal Pad GND Internally connected to GND. Used as a heatsink. Connect to the PCB GND plane
(1) I = input, O = output, I/O = input and output, GND = ground, P = power