SLVSH00 November   2024 TPD4S480

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—IEC Specification
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63-VDC Tolerant
      2. 6.3.2 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      3. 6.3.3 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      4. 6.3.4 EPR Adapter
        1. 6.3.4.1 VBUS Divider
        2. 6.3.4.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 EPR Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VBIAS Capacitor Selection
        2. 7.2.2.2 Dead Battery Operation
        3. 7.2.2.3 CC Line Capacitance
        4. 7.2.2.4 Additional ESD Protection on CC and SBU Lines
        5. 7.2.2.5 FLT Pin Operation
        6. 7.2.2.6 How to Connect Unused Pins
      3. 7.2.3 EPR Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1.     52

5.6 Timing Requirements

MIN NOM MAX UNIT
Power-On and Off Timings
tON_FET Time from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on. 1.3 3.5 ms
tON_FET_DB Time from Crossing Rising VPWR UVLO until CC and SBU OVP FETs are on and the dead battery resistors are off. 5.7 9.5 ms
dVPWR_OFF/dt Minimum slew rate for CC and FETs turn off during a power off. -0.5 V/µs
Over Voltage Protection
tOVP_RESPONSE_CC OVP response time on the CCx pins. Time from OVP asserted until OVP FETs turn off. 70 ns
tOVP_RESPONSE_SBU OVP response time on the SBUx pins. Time from OVP asserted until OVP FETs turn off.  80 ns
tOVP_RECOVERY_CC OVP recovery time on the CCx pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on. OVP must be removed for CC FETs to turn back on. 0.9 2.3 ms
tOVP_RECOVERY_CC_DB OVP recovery time on the CCx pins. Once an OVP has occurred, the minimum time duration until the CC FETs turn back on and the dead battery resistors turn off. OVP must be removed for CC FETs to turn back on.  5 ms
tOVP_RECOVERY_SBU OVP recovery time on the SBUx pins. Once an OVP has occurred, the minimum time duration until the SBU FETs turn back on. OVP must be removed for SBU FETs to turn back on.  0.62 ms
tOVP_FLT_ASSERTION Time from OVP Asserted to /FLT assertion. FLT assertion is 10% of the maximum value. Set C_CCx or C_SBUx above the maximum OVP threshold. Start the time where it passes the typical OVP threshold value. 20 µs
tOVP_FLT_DEASSERTION Time from CC FET turn on after an OVP to FLT deassertion. 5 ms