SLVSH09A November   2023  – June 2024 TPS6522005-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  System Control Thresholds
    6. 5.6  BUCK1 Converter
    7. 5.7  BUCK2, BUCK3 Converter
    8. 5.8  General Purpose LDOs (LDO1, LDO2)
    9. 5.9  General Purpose LDOs (LDO3, LDO4)
    10. 5.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 5.11 Voltage and Temperature Monitors
    12. 5.12 I2C Interface
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Power-Up Sequencing
      2. 6.3.2  Power-Down Sequencing
      3. 6.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 6.3.4  Reset to SoC (nRSTOUT)
      5. 6.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 6.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 6.3.6  Linear Regulators (LDO1 through LDO4)
      7. 6.3.7  Interrupt Pin (nINT)
      8. 6.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 6.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 6.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 6.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 6.3.12 I2C-Compatible Interface
        1. 6.3.12.1 Data Validity
        2. 6.3.12.2 Start and Stop Conditions
        3. 6.3.12.3 Transferring Data
    4. 6.4 Device Functional Modes
      1. 6.4.1 Modes of Operation
        1. 6.4.1.1 OFF State
        2. 6.4.1.2 INITIALIZE State
        3. 6.4.1.3 ACTIVE State
        4. 6.4.1.4 STBY State
        5. 6.4.1.5 Fault Handling
    5. 6.5 Multi-PMIC Operation
    6. 6.6 NVM Programming
      1. 6.6.1 TPS6522005-EP default NVM settings
      2. 6.6.2 NVM programming in Initialize State
      3. 6.6.3 NVM Programming in Active State
    7. 6.7 User Registers
    8. 6.8 Device Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Typical Application Example
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 7.2.3.2 LDO1, LDO2 Design Procedure
        3. 7.2.3.3 LDO3, LDO4 Design Procedure
        4. 7.2.3.4 VSYS, VDD1P8
        5. 7.2.3.5 Digital Signals Design Procedure
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4.1 Layout Guidelines

For all switching power supplies, the layout is an important step in the design. If the layout is not carefully done, the regulators can have stability and EMI issues. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitors, output capacitors, and inductors must be placed as close as possible to the device. The output capacitors must have a low impedance to ground. Use multiple VIAS (at least three) directly at the ground landing pad of the capacitor. Here are some layout guidelines:

  • PVIN_Bx: Place the input capacitor as close to the IC as allowed by the layout DRC rules. Any extra parasitic inductance between the input cap and the PVIN_Bx pin can create a voltage spike. It is recommended to have wide a short traces or polygon to help minimize trace inductance. Do not route any sensitive signals close to the input cap and the device pin as this node has high frequency switching currents. Add 3-4 vias per amp of current on the GND pads for each DCDC. If the space is limited and does not allow to place the input capacitors on the same layer as the PMIC, then place the input capacitors on the opposite layer with VIAS, close to the IC, and add a small input capacitor (0.1uF) on the same layer as the PMIC. This small capacitor must be placed close to the PVIN_Bx pin.
  • LX_Bx: Place the inductor close to the PMIC without compromising the PVIN input caps and use short & wide traces or polygons to connect the pin to the inductor. Do not route any sensitive signals close to this node. The inductor must be placed in the same layer as the IC to prevent having to use VIAS in the SW node. Since the SW-node voltage swings from the input voltage to ground with very fast rise and fall times, it is the main generator of EMI. If needed, to reduce EMI, a RC snubber can be added to the SW node.
  • FB_Bx: Route each of the FB_Bx pins as a trace to the output capacitor. Do not extend the output voltage polygon to the FB_Bx pin as this pin requires to be routed as a trace. The trace resistance from the output capacitor to the FB_Bx pin must be less than 1 Ω. The TPS6522005-EP does not support remote sensing so the FB_Bx pins must be connected to the local capacitor of the PMIC. Avoid routing the FB_Bx close to any noisy signals such as the switch node or under the inductor to avoid coupling. If space is constraint, FB_Bx pin can be routed through an inner layer. See example layout.
  • Bucks Cout: The local output capacitors must be placed as close to the inductor as possible to minimize electromagnetic emissions.
  • PVIN_LDOx: Place the input capacitor as close as possible to the PVIN_LDOx pin.
  • VLDOx: Place the output capacitor close to the VLDOx pin. For the LDO regulators, the feedback connection is internal. Therefore, it is important to keep the PCB resistance between LDO output and target load in the range of the acceptable voltage, IR, drop for LDOs.
  • VSYS: Connect VSYS directly to a quiet system voltage node. Place the decoupling capacitor as close as possible to the VSYS pin.
  • VDD1P8: Place the 2.2 uF cap as close as possible to the VDD1P8 pin. This capacitor needs to be placed in the same layer as the IC. Two to Three VIAS can be used to connect the GND side of the capacitor to the GND plane of the PCB.
  • Power Pad: The thermal pad must be connected to the PCB ground plane with a minimum of nine VIAS.
  • AGND: Do not connect AGND to the power pad (or thermal pad). The AGDN pin must be connected to the PCB ground planes through a VIA . Keep the trace from the AGDN pin to the VIA short.