SLVSH09A
November 2023 – June 2024
TPS6522005-EP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
System Control Thresholds
5.6
BUCK1 Converter
5.7
BUCK2, BUCK3 Converter
5.8
General Purpose LDOs (LDO1, LDO2)
5.9
General Purpose LDOs (LDO3, LDO4)
5.10
GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
5.11
Voltage and Temperature Monitors
5.12
I2C Interface
5.13
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power-Up Sequencing
6.3.2
Power-Down Sequencing
6.3.3
Push Button and Enable Input (EN/PB/VSENSE)
6.3.4
Reset to SoC (nRSTOUT)
6.3.5
Buck Converters (Buck1, Buck2, and Buck3)
6.3.5.1
Dual Random Spread Spectrum (DRSS)
6.3.6
Linear Regulators (LDO1 through LDO4)
6.3.7
Interrupt Pin (nINT)
6.3.8
PWM/PFM and Low Power Modes (MODE/STBY)
6.3.9
PWM/PFM and Reset (MODE/RESET)
6.3.10
Voltage Select pin (VSEL_SD/VSEL_DDR)
6.3.11
General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
6.3.12
I2C-Compatible Interface
6.3.12.1
Data Validity
6.3.12.2
Start and Stop Conditions
6.3.12.3
Transferring Data
6.4
Device Functional Modes
6.4.1
Modes of Operation
6.4.1.1
OFF State
6.4.1.2
INITIALIZE State
6.4.1.3
ACTIVE State
6.4.1.4
STBY State
6.4.1.5
Fault Handling
6.5
Multi-PMIC Operation
6.6
NVM Programming
6.6.1
TPS6522005-EP default NVM settings
6.6.2
NVM programming in Initialize State
6.6.3
NVM Programming in Active State
6.7
User Registers
6.8
Device Registers
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Typical Application Example
7.2.2
Design Requirements
7.2.3
Detailed Design Procedure
7.2.3.1
Buck1, Buck2, Buck3 Design Procedure
7.2.3.2
LDO1, LDO2 Design Procedure
7.2.3.3
LDO3, LDO4 Design Procedure
7.2.3.4
VSYS, VDD1P8
7.2.3.5
Digital Signals Design Procedure
7.2.4
Application Curves
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Support Resources
8.3
Trademarks
8.4
Electrostatic Discharge Caution
8.5
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
1
Features
Supports defense, aerospace, and medical applications
3
buck converters at up to 2.3 MHz switching frequency.
1× VIN: 2.5V – 5.5V; I
OUT
: 3.5A; V
OUT
0.6V – 3.4V
2× VIN: 2.5 V – 5.5 V; I
OUT
: 2A; V
OUT
0.6V – 3.4V
4
linear regulators:
2
x VIN: 1.5V – 5.5V; I
OUT
:
400
mA; V
OUT
: 0.6V – 3.4V (configurable as load switch and bypass-mode, supporting SD-card)
2
x VIN: 2.2V – 5.5V; I
OUT
: 300mA; V
OUT
: 1.2V – 3.3V (configurable as load switch)
Dynamic voltage scaling on all
three
buck converters
Low IQ/PFM, PWM-mode (quasi-fixed frequency)
or fixed frequency mode
Programmable power sequencing and default voltages
I
2
C interface, supporting standard, fast-mode and fast-mode+
Designed to support systems with
14
+ rails (2×
TPS6522005-EP
devices in multi-PMIC configuration)
2 GPOs
, 1 GPIO, and 3 multi-function-pins
EEPROM
programmability
Functional safety capable
Controlled baseline
One assembly/test site
One fabrication site
Extended product life cycle
Extended product-change notification
Product traceability