SLVSH40B November   2023  – August 2024 TPS92201 , TPS92201A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adaptive Off-time Control
      2. 7.3.2  Power Save Mode
      3. 7.3.3  Soft Startup
      4. 7.3.4  Low Dropout Operation
      5. 7.3.5  LED Current Setting
      6. 7.3.6  Voltage Reference
      7. 7.3.7  Switch Current Limit
      8. 7.3.8  Fault Behaviors
      9. 7.3.9  Under Voltage Lockout
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enabling/Disabling the Device
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting the Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input and Output Capacitor Selection
      3. 8.2.3 Application Performance Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

VIN = 2.5V to 5.5V, TA = –40°C to +85°C(TA = –55°C to +125°C for TPS92201MDRVR and TPS92201AMDRVR and for the TPS92201MDRLR and TPS92201AMDRLR); Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage range 2.5 5.5 V
VIN_UVLO VIN undervoltage lockout Fallng VIN 2.1 2.2 V
Rising VIN 2.3 2.4 V
Hysteresis 0.1 V
ISD Shutdown current into VIN VIN = 3.6V, VEN = 0 0.1 0.5 µA
ISD_ET Shutdown current into VIN VIN = 3.6V, VEN = 0 (TPS92201MDRVR,TPS92201AMDRVR, TPS92201MDRLR and TPS92201AMDRLR) 0.1 1.75 µA
IQ Quiescent current into VIN VIN = 3.6V, VEN = 2V, VFB=0V, Not switching (TPS92201) 450 520 600 µA
VIN = 3.6V, VEN = 2V, VFB = 0V, Not switching (TPS92201A) 520 630 720 µA
LOGIC INTERFACE
VEN_H High-level threshold voltage of EN 1.2 V
VEN_L Low-level threshold voltage of EN 0.4 V
VIH_PWM High-level threshold voltage of PWM 1 V
VIL_PWM Low-level threshold voltage of PWM 0.7 V
tEN_ON EN minimum on time to enable device µS
tEN_OFF EN minimum off time to disable device µS
tPWM_ON PWM minimum on time when dimming the output current  5 µS
fPWM PWM input frequency 20 200 kHz
DPWM PWM input duty cycle 1 100 %
ILKG Leakage current of EN pin VIN = 5.5V, VEN = 5.5V, VPWM = 5.5V, 1 µA
ILKG Leakage current of PWM pin VIN = 5.5V, VEN = 5.5V, VPWM = 5.5V, 0.5 µA
OUTPUT STAGE
VFB_REF FB pin regulation voltage at maximum duty cycle PWM = 100%, IOUT = 500mA 92 100 104 mV
FB pin regulation voltage at 50% duty cycle PWM = 50%, IOUT = 0mA(TM), FPWM=20KHz -8% 50 +8% mV
FB pin regulation voltage at 50% duty cycle PWM = 50%, IOUT = 0mA(TM), FPWM=200KHz -10% 50 +10% mV
FB pin regulation voltage at 5% duty cycle PWM = 5%, IOUT = 500mA 5 mV
FB pin regulation voltage at 1% duty cycle PWM = 1%, IOUT = 500mA 1 mV
RHS High-side FET on resistance 220 330 mΩ
RLS Low-side FET on resistance 170 300 mΩ
fSW Switching frequency 1.5 MHz
Dmax Maximum switching duty cycle 100 %
ILIM_HS High-side current limit 1.9 2.16 A