SLVSH68B June   2023  – June 2024 TPS543B25T

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Internal Linear Regulator and Bypassing
      3. 6.3.3  Enable and Adjustable UVLO
        1. 6.3.3.1 Internal Sequence of Events During Start-Up
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Remote Sense Amplifier and Adjusting the Output Voltage
      7. 6.3.7  Loop Compensation Guidelines
        1. 6.3.7.1 Output Filter Inductor Tradeoffs
        2. 6.3.7.2 Ramp Capacitor Selection
        3. 6.3.7.3 Output Capacitor Selection
        4. 6.3.7.4 Design Method for Good Transient Response
      8. 6.3.8  Soft Start and Prebiased Output Start-Up
      9. 6.3.9  MSEL Pin
      10. 6.3.10 Power Good (PG)
      11. 6.3.11 Output Overload Protection
        1. 6.3.11.1 Positive Inductor Current Protection
        2. 6.3.11.2 Negative Inductor Current Protection
      12. 6.3.12 Output Overvoltage and Undervoltage Protection
      13. 6.3.13 Overtemperature Protection
      14. 6.3.14 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2  Switching Frequency
          3. 7.2.1.2.3  Output Inductor Selection
          4. 7.2.1.2.4  Output Capacitor
          5. 7.2.1.2.5  Input Capacitor
          6. 7.2.1.2.6  Adjustable Undervoltage Lockout
          7. 7.2.1.2.7  Output Voltage Resistors Selection
          8. 7.2.1.2.8  Bootstrap Capacitor Selection
          9. 7.2.1.2.9  VDRV and VCC Capacitor Selection
          10. 7.2.1.2.10 PGOOD Pullup Resistor
          11. 7.2.1.2.11 Current Limit Selection
          12. 7.2.1.2.12 Soft-Start Time Selection
          13. 7.2.1.2.13 Ramp Selection and Control Loop Stability
          14. 7.2.1.2.14 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

9 Revision History

Changes from Revision A (April 2024) to Revision B (June 2024)

  • Changed ILS(OC1) MIN from 27.8 to 26.1Go
  • Changed ILS(OC1) MAX from 30.2 to 31.9Go
  • Changed ILS(OC2) MIN from 22.1 to 21.15Go
  • Changed ILS(OC2) MAX from 24.4 to 25.85Go

Changes from Revision * (June 2023) to Revision A (April 2024)

  • Changed the document status from Advance Information to Production DataGo