As for all switching power supplies, especially those running at high switching frequency and high current, layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to minimize interplane coupling.

The most critical current path for this converter is from the external low side MOSFET to the integrated high side MOSFET, then to the VOUT side capacitors, and back to the source of the external low side MOSFET. This current path contains nanosecond rise and fall times and must be kept as short as possible to reduce the parasitic inductance. Therefore, the VOUT side output capacitors must be close not only to the VOUT pin, but also to the source pin of the external low side MOSFET to reduce the spike at the SW pin and the VOUT pin.

The PGND plane and the AGND plane are connected at the terminal of the VCC capacitor. Thus the noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal control circuit.

The layout should also be done with well consideration of the thermal as this is a high power density device. The SW, VOUT, and PGND pins that improves the thermal capabilities of the package should be soldered with the large polygon, using thermal vias underneath the SW pin could improve thermal performance.