SLVSHB5A October   2024  – November 2024 TPS61287

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Start-up
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Programmable EN/UVLO
      4. 6.3.4 Switching Valley Current Limit
      5. 6.3.5 External Clock Synchronization
      6. 6.3.6 Stackable Multi-phase Operation
      7. 6.3.7 Device Functional Modes
        1. 6.3.7.1 Forced PWM Mode
        2. 6.3.7.2 Auto PFM Mode
      8. 6.3.8 Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap And VCC Capacitors Selection
        4. 7.2.2.4 MOSFET Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.7 Loop Stability

The TPS61287 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.

The power stage small signal loop response of constant on-time (COT) with peak current control can be modeled by Equation 11.

Equation 11. TPS61287

where

  • D is the switching duty cycle.
  • RO is the output load resistance.
  • KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 20A/V.
Equation 12. TPS61287

where

  • CO is output capacitor.
Equation 13. TPS61287

where

  • RESR is the equivalent series resistance of the output capacitor.
Equation 14. TPS61287

The COMP pin is the output of the internal transconductance amplifier. Equation 15 shows the small signal transfer function of compensation network.

Equation 15. TPS61287

where

  • GEA is the transconductance of the amplifier.
  • REA is the output resistance of the amplifier.
  • VREF is the reference voltage at the FB pin.
  • VOUT is the output voltage.
  • ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
  • ƒCOMZ is the zero's frequency of the compensation network.

The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.

Then set the value of RC, CC, and CP (in ) by following these equations.

Equation 16. TPS61287

where

  • ƒC is the selected crossover frequency.

The value of CC can be set by Equation 17.

Equation 17. TPS61287

The value of CP can be set by Equation 18.

Equation 18. TPS61287

If the calculated value of CP is less than 10pF, it can be left open.

Designing the loop for greater than 45° of phase margin and greater than 10dB gain margin eliminates output voltage ringing during the line and load transient.