SLVSHB5A October   2024  – November 2024 TPS61287

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable and Start-up
      2. 6.3.2 Undervoltage Lockout (UVLO)
      3. 6.3.3 Programmable EN/UVLO
      4. 6.3.4 Switching Valley Current Limit
      5. 6.3.5 External Clock Synchronization
      6. 6.3.6 Stackable Multi-phase Operation
      7. 6.3.7 Device Functional Modes
        1. 6.3.7.1 Forced PWM Mode
        2. 6.3.7.2 Auto PFM Mode
      8. 6.3.8 Overvoltage Protection
      9. 6.3.9 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap And VCC Capacitors Selection
        4. 7.2.2.4 MOSFET Selection
        5. 7.2.2.5 Input Capacitor Selection
        6. 7.2.2.6 Output Capacitor Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 3.6V and VOUT = 18V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 2.0 23 V
VOUT Output voltage range 4.5 25 V
VIN_UVLO Under voltage lockout threshold at VIN VIN_UVLO rising 2.2 2.3 V
VIN_UVLO Under voltage lockout threshold at VIN VIN_UVLO falling 1.9 2.0 V
VCC Internal regulator output IVCC = 15 mA 5.1 V
VCC_UVLO VCC UVLO threshold VCC rising 2.3 V
VCC_UVLO VCC UVLO threshold VCC falling 2.15 V
IQ_VIN Quiescent current into VIN pin EN = High, No switching, 2.5V<VIN<5.5V,  VFB = VREF + 0.1V, TJ up to 85°C 3 13 µA
IQ_VIN Quiescent current into VIN pin EN = High, No switching, 6.5V<VIN<23V,  VFB = VREF + 0.1V, TJ up to 85°C 200 250 uA

IQ_VOUT		 Quiescent current into VOUT pin EN = High, No switching, 2.5V<VIN<5.5V,  VFB = VREF + 0.1V, TJ up to 85°C 210 260 µA

IQ_VOUT		 Quiescent current into VOUT pin EN = High, No switching, 6.5V<VIN<23V,  VFB = VREF + 0.1V, TJ up to 85°C 30 60 uA
IQ_SW Quiescent current into SW pin EN = High, No switching, 2.5V<VIN<23V, VOUT > VIN, VFB = VREF + 0.1V, TJ up to 85°C 2.5 5.0 µA

ISD_VIN
 		 Shutdown current into VIN pin  IC disabled, VIN = SW = 2.5V to 23V, TJ up to 85°C 1.5 7 µA
ISD_SW Shutdown current into SW pin IC disabled, VIN = SW = 2.5V to 23V, TJ up to 85°C 0.25 2 µA

ISD_VOUT		 Shutdown current into VOUT pin IC disabled, VOUT = 2.5V to 25V, VIN=0V, TJ up to 85°C 2.5 6 µA
IFB_LKG Leakage current into FB pin 50 nA
LOGIC INTERFACE
VEN_H EN high-level voltage threshold VCC = 5.0V 1.18 V
VEN_L EN low-level voltage threshold VCC = 5.0V 0.4 V
VEN/UVLO_RISE UVLO rising threshold at the EN/UVLO VCC = 5.0V 1.20 1.23 1.27 V
IEN/UVLO Sourcing current at the EN/UVLO pin VEN/UVLO=1.3V 5.3 µA
VMODE_H MODE high-level voltage threshold VCC = 5.0V 1.2 V
VMODE_L MODE low-level voltage threshold VCC = 5.0V 0.4 V
OUTPUT
VREF Reference voltage at the FB pin PWM mode 0.985 1 1.015 V
VREF Reference voltage at the FB pin PFM mode 1.01 V
VOUT_OVP Output OVP protection threshold VOUT OVP rising 25.7 27 28 V
VOUT_OVP_HYS Output OVP protection hysteresis 1 V
POWER SWITCH
RDS(on) High-side MOSFET on resistance VCC = 5.0V 8.5 mΩ

FSW		 Switching frequency VIN = 3.6V, VOUT= 18V, PWM mode 285 320 355 kHz
tOFF_min Minimum off time 90 130 ns
tDLH LS-GATE off  to HS-GATE on deadtime 30 ns
tDHL HS-GATE off to LS-GATE on deadtime 25 ns

ILIM
 		 High clamp valley current limit RILIM = 20kΩ , Forced PWM mode 17 20 23 A

ILIM
 		 High clamp valley current limit RILIM = 20kΩ , Auto PFM mode 17 20 23 A

ILIM
 		 Low clamp valley current limit  0.25 A
SOFT START
tSS Soft start time of internal reference 7 ms
GATE DRIVER
VDRV_L Low-state voltage drop 100-mA sinking 0.045 V
VDRV_H High-state voltage drop 100-mA sourcing 0.12 V
ERROR AMPLIFIER
ISINK COMP pin sink current VFB = VREF + 400mV, VCOMP = 1.5V 20 µA
ISOURCE COMP pin source current VFB = VREF - 400mV, VCOMP = 1.5V 20 µA
VCOMPH High clamp voltage at the COMP pin RILIM = 20kΩ , PWM mode 1.6 V
VCOMPH High clamp voltage at the COMP pin RILIM = 20kΩ , PFM mode 1.45 V
VCOMPL Low clamp voltage at the COMP pin 0.6 V
KCOMP Power stage trans-conductance
(inductor peak current / comp voltage)		 20 A/V
GEA Error amplifier transconductance VCC = 5.0V 180 µA/V
SYNCHRONOUS CLOCK
RSYNC Internal pull down resistor from SYNC pin 800 kΩ
VM/SYNC_H M/SYNC high-level voltage threshold 1.2 V
VM/SYNC_L M/SYNC low-level voltage threshold 0.4 V
TSYNC_MIN Minimum sync clock pulse width 50 ns
PROTECTION
TSD Thermal shutdown Junction temperature rising 160 °C
TSD_HYS Thermal shutdown hysteresis 20 °C