SLVSHI2A February   2024  – April 2024 LP5867

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
        1. 7.3.2.1 Global 3-Bits Maximum Current (MC) Setting
        2. 7.3.2.2 3 Groups of 7-Bits Color Current (CC) Setting
        3. 7.3.2.3 Individual 8-bit Dot Current (DC) Setting
      3. 7.3.3 PWM Dimming
        1. 7.3.3.1 Individual 8-Bit / 16-Bit PWM for Each LED Dot
        2. 7.3.3.2 Programmable Groups of 8-Bit PWM Dimming
        3. 7.3.3.3 8-Bit PWM for Global Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
        1. 7.3.7.1 LED Open Detection
        2. 7.3.7.2 LED Short Detection
        3. 7.3.7.3 Thermal Shutdown
        4. 7.3.7.4 UVLO (Under Voltage Lock Out)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Interface Selection
      2. 7.5.2 I2C Interface
        1. 7.5.2.1 I2C Data Transactions
        2. 7.5.2.2 I2C Data Format
        3. 7.5.2.3 Multiple Devices Connection
      3. 7.5.3 Programming
        1. 7.5.3.1 SPI Data Transactions
        2. 7.5.3.2 SPI Data Format
        3. 7.5.3.3 Multiple Devices Connection
    6. 7.6 Register Maps
  9. 8 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Program Procedure
      4. 9.2.4 Application Performance Plots
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 VDD Input Supply Recommendations
      2. 9.3.2 VLED Input Supply Recommendations
      3. 9.3.3 VIO Input Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

GUID-20230817-SS0I-KZZL-KBRX-BJQ98Q8FGZR9-low.svgFigure 5-1 LP5867 YBH Package 24-Pin WCSP Top View
Table 5-1 Pin Functions
PINI/ODESCRIPTION
NO.NAME
C2CSR0OCurrent sink 0. If not used, this pin must be floating.
B2CSG0OCurrent sink 1. If not used, this pin must be floating.
B3CSB0OCurrent sink 2. If not used, this pin must be floating.
B5CSR1OCurrent sink 3. If not used, this pin must be floating.
C5CSG1OCurrent sink 4. If not used, this pin must be floating.
C4CSB1OCurrent sink 5. If not used, this pin must be floating.
A1SW0OHigh-side PMOS switch output for scan line 0. If not used, this pin must be floating.
A2SW1OHigh-side PMOS switch output for scan line 1. If not used, this pin must be floating.
A3SW2OHigh-side PMOS switch output for scan line 2. If not used, this pin must be floating.
A4SW3OHigh-side PMOS switch output for scan line 3. If not used, this pin must be floating.
A5SW4OHigh-side PMOS switch output for scan line 4. If not used, this pin must be floating.
A6SW5OHigh-side PMOS switch output for scan line 5. If not used, this pin must be floating.
B6SW6OHigh-side PMOS switch output for scan line 6. If not used, this pin must be floating.
B1VLEDPowerPower input for high-side switches.
B4GNDGroundMust be connected to common ground plane.
D2VCAPOInternal LDO output. An 1μF capacitor must be connected between this pin with GND. Place the capacitor as close to the device as possible.
C3IFSIInterface type select. I2C is selected when IFS is low. SPI is selected when IFS is high. A resistor must be connected between VIO and this pin.
C6VSYNCIExternal synchronize signal for display mode 2 and mode 3.
D6SCL/SCLKII2C clock input or SPI clock input. Pull up to VIO when configured as I2C.
D5SDA/MOSII/OI2C data input or SPI leader output follower input. Pull up to VIO when configured as I2C.
D4ADDR0/MISOI/OI2C address select 0 or SPI leader input follower output.
D3ADDR1/SSII2C address select 1 or SPI follower select.
D1VIO/ENPower,IPower supply for digital circuits and chip enable. An 1nF capacitor must be connected between this pin with GND and be placed as close to the device as possible.
C1VCCPowerPower supply for device. A 1μF capacitor must be connected between this pin with GND and be placed as close to the device as possible.