SLVSHI5
April 2024
TPS23881B
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
5.1
Detailed Pin Description
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Parameter Measurement Information
7.1
Timing Diagrams
8
Detailed Description
8.1
Overview
8.1.1
Operating Modes
8.1.1.1
Auto
8.1.1.2
Semiauto
8.1.1.3
Manual and Diagnostic
8.1.1.4
Power Off
8.1.2
PoE Compliance Terminology
8.1.3
Channel versus Port Terminology
8.1.4
Requested Class versus Assigned Class
8.1.5
Power Allocation and Power Demotion
8.1.6
Programmable SRAM
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Port Remapping
8.3.2
Port Power Priority
8.3.3
Analog-to-Digital Converters (ADC)
8.3.4
I2C Watchdog
8.3.5
Current Foldback Protection
8.4
Device Functional Modes
8.4.1
Detection
8.4.2
Connection Check
8.4.3
Classification
8.4.4
DC Disconnect
8.5
I2C Programming
8.5.1
I2C Serial Interface
8.6
Register Maps
8.6.1
Complete Register Set
8.6.2
Detailed Register Descriptions
8.6.2.1
INTERRUPT Register
8.6.2.2
INTERRUPT MASK Register
8.6.2.3
POWER EVENT Register
8.6.2.4
DETECTION EVENT Register
8.6.2.5
FAULT EVENT Register
8.6.2.6
START/ILIM EVENT Register
8.6.2.7
SUPPLY and FAULT EVENT Register
8.6.2.7.1
Detected SRAM Faults and "Safe Mode"
8.6.2.8
CHANNEL 1 DISCOVERY Register
8.6.2.9
CHANNEL 2 DISCOVERY Register
8.6.2.10
CHANNEL 3 DISCOVERY Register
8.6.2.11
CHANNEL 4 DISCOVERY Register
8.6.2.12
POWER STATUS Register
8.6.2.13
PIN STATUS Register
8.6.2.14
OPERATING MODE Register
8.6.2.15
DISCONNECT ENABLE Register
8.6.2.16
DETECT/CLASS ENABLE Register
8.6.2.17
Power Priority / 2Pair PCUT Disable Register Name
8.6.2.18
TIMING CONFIGURATION Register
8.6.2.19
GENERAL MASK Register
8.6.2.20
DETECT/CLASS RESTART Register
8.6.2.21
POWER ENABLE Register
8.6.2.22
RESET Register
8.6.2.23
ID Register
8.6.2.24
Connection Check and Auto Class Status Register
8.6.2.25
2-Pair Police Ch-1 Configuration Register
8.6.2.26
2-Pair Police Ch-2 Configuration Register
8.6.2.27
2-Pair Police Ch-3 Configuration Register
8.6.2.28
2-Pair Police Ch-4 Configuration Register
8.6.2.29
Capacitance (Legacy PD) Detection
8.6.2.30
Power-on Fault Register
8.6.2.31
PORT RE-MAPPING Register
8.6.2.32
Channels 1 and 2 Multi Bit Priority Register
8.6.2.33
Channels 3 and 4 Multi Bit Priority Register
8.6.2.34
4-Pair Wired and Port Power Allocation Register
8.6.2.35
4-Pair Police Ch-1 and 2 Configuration Register
8.6.2.36
4-Pair Police Ch-3 and 4 Configuration Register
8.6.2.37
TEMPERATURE Register
8.6.2.38
4-Pair Fault Configuration Register
8.6.2.39
INPUT VOLTAGE Register
8.6.2.40
CHANNEL 1 CURRENT Register
8.6.2.41
CHANNEL 2 CURRENT Register
8.6.2.42
CHANNEL 3 CURRENT Register
8.6.2.43
CHANNEL 4 CURRENT Register
8.6.2.44
CHANNEL 1 VOLTAGE Register
8.6.2.45
CHANNEL 2 VOLTAGE Register
8.6.2.46
CHANNEL 3 VOLTAGE Register
8.6.2.47
CHANNEL 4 VOLTAGE Register
8.6.2.48
2x FOLDBACK SELECTION Register
8.6.2.49
FIRMWARE REVISION Register
8.6.2.50
I2C WATCHDOG Register
8.6.2.51
DEVICE ID Register
8.6.2.52
CHANNEL 1 DETECT RESISTANCE Register
8.6.2.53
CHANNEL 2 DETECT RESISTANCE Register
8.6.2.54
CHANNEL 3 DETECT RESISTANCE Register
8.6.2.55
CHANNEL 4 DETECT RESISTANCE Register
8.6.2.56
CHANNEL 1 DETECT CAPACITANCE Register
8.6.2.57
CHANNEL 2 DETECT CAPACITANCE Register
8.6.2.58
CHANNEL 3 DETECT CAPACITANCE Register
8.6.2.59
CHANNEL 4 DETECT CAPACITANCE Register
8.6.2.60
CHANNEL 1 ASSIGNED CLASS Register
8.6.2.61
CHANNEL 2 ASSIGNED CLASS Register
8.6.2.62
CHANNEL 3 ASSIGNED CLASS Register
8.6.2.63
CHANNEL 4 ASSIGNED CLASS Register
8.6.2.64
AUTO CLASS CONTROL Register
8.6.2.65
CHANNEL 1 AUTO CLASS POWER Register
8.6.2.66
CHANNEL 2 AUTO CLASS POWER Register
8.6.2.67
CHANNEL 3 AUTO CLASS POWER Register
8.6.2.68
CHANNEL 4 AUTO CLASS POWER Register
8.6.2.69
ALTERNATIVE FOLDBACK Register
8.6.2.70
SRAM CONTROL Register
8.6.2.70.1
SRAM START ADDRESS (LSB) Register
8.6.2.70.2
SRAM START ADDRESS (MSB) Register
9
Application and Implementation
9.1
Application Information
9.1.1
Introduction to PoE
9.1.1.1
2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Connections on Unused Channels
9.2.2.2
Power Pin Bypass Capacitors
9.2.2.3
Per Port Components
9.2.2.4
System Level Components (not Shown in the Schematic Diagrams)
9.2.3
Application Curves
9.3
Power Supply Recommendations
9.3.1
VDD
9.3.2
VPWR
9.4
Layout
9.4.1
Layout Guidelines
9.4.1.1
Kelvin Current Sensing Resistors
9.4.2
Layout Example
9.4.2.1
Component Placement and Routing Guidelines
9.4.2.1.1
Power Pin Bypass Capacitors
9.4.2.1.2
Per-Port Components
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
9.4
Layout