The system TVS and bulk VPWR capacitance work together to protect the PSE system from surge events which can cause VPWR to surge above 70 V. The TVS and bulk capacitors must be placed on the PCB such that all TPS23881B ports are adequately protected.
- TVS: The system TVS must be rated for the expected peak surge power of the system and have a minimum reverse standoff voltage of 58 V. Together with the VPWR bulk capacitance, the TVS must prevent the VPWR rail from exceeding 70 V.
- Bulk Capacitor: The system bulk capacitors must be rated for 100 V and can be of aluminum electrolytic type. Two 47-μF capacitors can be used for each TPS23881B on board.
- Distributed Capacitance: In higher port
count systems, it may be necessary to distribute 1-uF, 100-V, X7R ceramic
capacitors across the 54-V power bus. TI recommends one capacitor per each TPS23881B pair.
- Digital I/O Pullup Resistors:RESET and A1-A4 are internally pulled up to VDD, while OSS is internally pulled down, each with a 50-kΩ (typical) resistor. A stronger pullup and down resistor can be added externally such as a 10 kΩ, 1%, 0.063 W type in a SMT package. SCL, SDAI, SDAO, and INT require external pullup resistors within a range of 1 kΩ to 10 kΩ depending on the total number of devices on the bus.
- Ethernet Data Transformer (Per Port): The Ethernet data transformer must be rated to operate within the IEEE802.3bt standard in the presence of the DC port current conditions. The transformer is also chosen to be compatible with the Ethernet PHY. The transformer may also be integrated into the RJ45 connector and cable terminations.
- RJ45 Connector (Per Port): The majority of the RJ45 connector requirements are mechanical in nature and include tab orientation, housing type (shielded or unshielded), or highly integrated. An integrated RJ45 consists of the Ethernet data transformer and cable terminations at a minimum. The integrated type may also contain the port TVS and common mode EMI filtering.
- Cable Terminations (Per Port): The cable terminations typically consist of series resistor (usually 75 Ω) and capacitor (usually 10 nF) circuits from each data transformer center tap to a common node which is then bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pF to 4700 pF at 2 kV).