SLVSHI5 April   2024 TPS23881B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1. 5.1 Detailed Pin Description
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Operating Modes
        1. 8.1.1.1 Auto
        2. 8.1.1.2 Semiauto
        3. 8.1.1.3 Manual and Diagnostic
        4. 8.1.1.4 Power Off
      2. 8.1.2 PoE Compliance Terminology
      3. 8.1.3 Channel versus Port Terminology
      4. 8.1.4 Requested Class versus Assigned Class
      5. 8.1.5 Power Allocation and Power Demotion
      6. 8.1.6 Programmable SRAM
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 Analog-to-Digital Converters (ADC)
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Current Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Detection
      2. 8.4.2 Connection Check
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 I2C Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 Complete Register Set
      2. 8.6.2 Detailed Register Descriptions
        1. 8.6.2.1  INTERRUPT Register
        2. 8.6.2.2  INTERRUPT MASK Register
        3. 8.6.2.3  POWER EVENT Register
        4. 8.6.2.4  DETECTION EVENT Register
        5. 8.6.2.5  FAULT EVENT Register
        6. 8.6.2.6  START/ILIM EVENT Register
        7. 8.6.2.7  SUPPLY and FAULT EVENT Register
          1. 8.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 8.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 8.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 8.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 8.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 8.6.2.12 POWER STATUS Register
        13. 8.6.2.13 PIN STATUS Register
        14. 8.6.2.14 OPERATING MODE Register
        15. 8.6.2.15 DISCONNECT ENABLE Register
        16. 8.6.2.16 DETECT/CLASS ENABLE Register
        17. 8.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 8.6.2.18 TIMING CONFIGURATION Register
        19. 8.6.2.19 GENERAL MASK Register
        20. 8.6.2.20 DETECT/CLASS RESTART Register
        21. 8.6.2.21 POWER ENABLE Register
        22. 8.6.2.22 RESET Register
        23. 8.6.2.23 ID Register
        24. 8.6.2.24 Connection Check and Auto Class Status Register
        25. 8.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 8.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 8.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 8.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 8.6.2.29 Capacitance (Legacy PD) Detection
        30. 8.6.2.30 Power-on Fault Register
        31. 8.6.2.31 PORT RE-MAPPING Register
        32. 8.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 8.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 8.6.2.34 4-Pair Wired and Port Power Allocation Register
        35. 8.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 8.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
        37. 8.6.2.37 TEMPERATURE Register
        38. 8.6.2.38 4-Pair Fault Configuration Register
        39. 8.6.2.39 INPUT VOLTAGE Register
        40. 8.6.2.40 CHANNEL 1 CURRENT Register
        41. 8.6.2.41 CHANNEL 2 CURRENT Register
        42. 8.6.2.42 CHANNEL 3 CURRENT Register
        43. 8.6.2.43 CHANNEL 4 CURRENT Register
        44. 8.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 8.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 8.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 8.6.2.47 CHANNEL 4 VOLTAGE Register
        48. 8.6.2.48 2x FOLDBACK SELECTION Register
        49. 8.6.2.49 FIRMWARE REVISION Register
        50. 8.6.2.50 I2C WATCHDOG Register
        51. 8.6.2.51 DEVICE ID Register
        52. 8.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 8.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 8.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 8.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
        56. 8.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 8.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 8.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 8.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
        60. 8.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 8.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 8.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 8.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
        64. 8.6.2.64 AUTO CLASS CONTROL Register
        65. 8.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 8.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 8.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 8.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
        69. 8.6.2.69 ALTERNATIVE FOLDBACK Register
        70. 8.6.2.70 SRAM CONTROL Register
          1. 8.6.2.70.1 SRAM START ADDRESS (LSB) Register
          2. 8.6.2.70.2 SRAM START ADDRESS (MSB) Register
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
        1. 9.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Connections on Unused Channels
        2. 9.2.2.2 Power Pin Bypass Capacitors
        3. 9.2.2.3 Per Port Components
        4. 9.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 VDD
      2. 9.3.2 VPWR
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Kelvin Current Sensing Resistors
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Component Placement and Routing Guidelines
          1. 9.4.2.1.1 Power Pin Bypass Capacitors
          2. 9.4.2.1.2 Per-Port Components
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1.6 Programmable SRAM

The TPS23881B device has been designed to include programmable SRAM that accommodates future firmware updates to support interoperability and/or compliance issues that may arise as new equipment is introduced in conjunction with the release of the IEEE 802.3bt standard.

Note:

The latest version of firmware and SRAM release notes may be accessed from the TI mySecure Software webpage.

The SRAM Release Notes and ROM Advisory document includes more detailed information regarding any know issues and changes that were associated with each firmware release.

Upon power up, TI recommends that the SRAM of the TPS23881B device be programmed with the latest version of SRAM code via I2C to ensure proper operation and IEEE complaint performance. All I2C traffic other than those commands required to program the SRAM must be deferred until after the SRAM programming sequences are completed.

For systems that include multiple TPS23881B devices, the 0x7F "global" broadcast I2C address may be used to programmed all of the devices at the same time.

For more detailed instructions on the SRAM programing procedures please refer to SRAM Control Register and the How to Load TPS2388x SRAM and Parity Code Over I 2C application brief on TI.com.