SLVU380A September   2010  – October 2021 TPS54320

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Set Point
      2. 1.3.2 Slow Start Time
      3. 1.3.3 Track In
      4. 1.3.4 Adjustable UVLO
      5. 1.3.5 Input Voltage Rails
  3. 2Test Setup and Results
    1. 2.1  Input / Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Output Voltage Line Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristics
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Powering Up
    10. 2.10 Thermal Characteristics
  4. 3Board Layout
    1. 3.1 Layout
    2. 3.2 Estimated Circuit Area
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

2.9 Powering Up

Figure 2-9 and Figure 2-10 show the start-up waveforms for the TPS54320. In Figure 2-9, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor divider network. In Figure 2-10, the input voltage is initially applied and the output is inhibited by using a jumper at JP2 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of 3.3 V. The input voltage for these plots is 12 V and the load is 1.1Ω.

GUID-63BB8337-59BD-4771-AF05-41733F3136B3-low.gifFigure 2-9 TPS54320 Start-Up Relative to VIN
GUID-E5B7A5A8-5B34-4DDC-B26D-710BD125D926-low.gifFigure 2-10 TPS54320 Start-Up Relative to Enable