The board layout for the TPS54821EVM-049 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.

The top layer contains the main power traces for PVIN, VIN, V_OUT, and VPHASE. Also on the top layer are connections for the remaining pins of the TPS54821 and a large area filled with ground. The internal layer-2 is primarily ground with additional fill areas for PVIN, VIN, and V_OUT. The bottom and internal layer-2 contain ground planes only. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board including five vias directly under the TPS54821 device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.

The input decoupling capacitors (C2 and C4) and bootstrap capacitor (C5) are all located as close to the IC as possible. Additionally, the voltage setpoint resistor divider components are kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper V_OUT trace at the J4 output connector. For the TPS54821, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply. Critical analog circuits such as the voltage setpoint divider, frequency set resistor, slow-start capacitor, and compensation components are terminated to ground using a wide ground trace separate from the power ground pour.

Figure 3-1 TPS54821EVM-049 Top-Side Assembly

Figure 3-2 TPS54821EVM-049 Top-Side Layout

Figure 3-3 TPS54821EVM-049 Internal Layer-1 Layout

Figure 3-4 TPS54821EVM-049 Internal Layer-2 Layout

Figure 3-5 TPS54821EVM-049 Bottom-Side Layout