SLVU777A September   2012  – November 2021 TPS54020

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Specification Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Slow-Start Time
      3. 1.3.3 Adjustable UVLO
      4. 1.3.4 Input Voltage Rails
  3. 2Test Setup and Results
    1. 2.1  Input / Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Output Voltage Line Regulation
    5. 2.5  Load Transient
    6. 2.6  Control Loop Response
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Start Up
    10. 2.10 Pre-Bias Start Up
    11. 2.11 Hiccup Mode Current Limit
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

2.1 Input / Output Connections

The EVM is provided with input/output connectors and test points as shown in Table 2-1. A power supply capable of supplying 5 A must be connected to J1, and a pair of 20-AWG wires is recommended. The jumper across J2 must be in place across pins 1 and 2. See Section 1.3.4 for split-input voltage rail operation. The load must be connected to J3 and a pair of 20-AWG wires is recommended. The load must be capable of drawing 10 A at 1.8 V. Wire lengths should be minimized to reduce losses in the wires. Test-point TP1 provides a place to monitor the PVIN input voltages with TP6 providing a convenient ground reference. TP5 is used to monitor the output voltage with TP8 as the ground reference.

Table 2-1 EVM Connectors and Test Points
Reference DesignatorFunction
J1PVIN input voltage connector. (See Table 1-1 for VIN range.)
J2PVIN to VIN jumper. Shunt SH1 is normally connected from pin 1 to pin 2 to tie VIN to PVIN for common rail voltage operation.
J3VOUT, 1.8 V at 10-A maximum.
J4VIN input voltage connector. Not normally used.
J52-pin header for enable. Connect EN to ground to disable, open to enable.
J62-pin header used to for sequencing via the slow start voltage.
TP1Test point for PVIN.
TP2Test point for Power Good. Biased from VOUT.
TP3Test point for SYNC OUT. In RT mode, this is a clock output. In SYNC mode, this is a digital input.
TP4Test point for VIN.
TP5Test point for VOUT.
TP6Test point for PGND, near input.
TP7Test point for PH, or Switch Node.
TP8Test point for PGND, near output.
TP9Test point between voltage divider network and output. Used for loop response measurements.
TP10Test point for ENABLE.
TP11Test point for the timing resistor RT and Clock.
TP12Test point for slow start.
TP13Test point for AGND.
TP14Test point for AGND.