SLVUAA3A August   2014  – July 2021 TPS563200

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Setpoint
  5. 4Test Setup and Results
    1. 4.1  Input/Output Connections
    2. 4.2  Start-Up Procedure
    3. 4.3  Efficiency
    4. 4.4  Load Regulation
    5. 4.5  Line Regulation
    6. 4.6  Load Transient Response
    7. 4.7  Output Voltage Ripple
    8. 4.8  Input Voltage Ripple
    9. 4.9  Start-Up
    10. 4.10 Shut-Down
  6. 5Board Layout
    1. 5.1 Layout
  7. 6Schematic, Bill of Materials, and Reference
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
    3. 6.3 Reference
  8. 7Revision History

5.1 Layout

The board layout for the TPS563200EVM-652 is shown in Figure 5-1, Figure 5-2 and Figure 5-3. The top layer contains the main power traces for VIN, VOUT, and ground. Also on the top layer are connections for the pins of the TPS563200 and a large area filled with ground. Most of the signal traces are also located on the top side. The input decoupling capacitors, C1, C2, and C3 are located as close to the IC as possible. The input and output connectors, test points, and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, signal ground copper fill and the feed back trace from the point of regulation to the top of the resistor divider network.

Figure 5-1 Top Assembly
Figure 5-2 Top Layer
Figure 5-3 Bottom Layer