SLVUAM8B December   2015  – August 2021 TPS54A20

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
    2. 1.2 Background
    3. 1.3 Performance Specification Summary
    4. 1.4 Modifications
      1. 1.4.1 Output Voltage Setpoint
      2. 1.4.2 On Time
      3. 1.4.3 Adjustable UVLO
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Output Voltage Line Regulation
    5. 2.5  Load Transients
    6. 2.6  Loop Characteristics
    7. 2.7  Output Voltage Ripple
    8. 2.8  Input Voltage Ripple
    9. 2.9  Powering Up
    10. 2.10 Thermal Image
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

3.1 Layout

The board layout for the TPS54A20EVM-770 is shown in Figure 3-1 through Figure 3-5. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.

The top layer contains the main power traces for VIN, VOUT, SWA and SWB. Also on the top layer are connections for the remaining pins of the TPS54A20 and a large area filled with ground. The internal layer-1 is dedicated ground plane. The internal layer-2 contain an additional large ground copper area as well as an additional VOUT copper fill. The bottom layer is another ground plane with an additional trace for the output voltage feedback. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board including five vias directly under the TPS54A20 device to provide a thermal path from the top-side ground plane to the bottom-side ground plane.

The input decoupling capacitors and bootstrap capacitor are all located as close to the IC as possible. Additionally, the voltage setpoint resistor divider components are kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the TP7 test point. For the TPS54A20, an additional input bulk capacitor may be required, depending on the EVM connection to the input supply. Critical analog circuits such as the voltage set point divider, frequency set resistor, and compensation components are terminated to ground using a wide ground trace separate from the power ground pour.

Figure 3-1 TPS54A20EVM-770 Top-Side Assembly
Figure 3-3 TPS54A20EVM-770 Internal Layer-1 Layout
Figure 3-5 TPS54A20EVM-770 Bottom-Side Layout
Figure 3-2 TPS54A20EVM-770 Top-Side Layout
Figure 3-4 TPS54A20EVM-770 Internal Layer-2 Layout