SLVUB50C June   2017  – March 2019 UCD90120A , UCD90124A , UCD90160 , UCD90160A , UCD90240 , UCD90320 , UCD90320U , UCD9090 , UCD9090-Q1 , UCD9090A , UCD90910

 

  1.   UCD90xxx Sequencer Schematics Guidelines
    1. 1 Introduction
    2. 2 UCD Power Supply Review
      1. 2.1 UCD90240, UCD90320 and UCD90320U
      2. 2.2 Remaining UCD90xxx Devices
    3. 3 I/O Signals Review
      1. 3.1 Analog Monitor (MONx/AMONx) Pin Review
      2. 3.2 PMBUS Signals Review
      3. 3.3 GPIO Pins Review
      4. 3.4 Margin Pins Review
      5.      Trademarks
  2.   Revision History

3.3 GPIO Pins Review

Consider the initial I/O states detailed in Table 2 when the device is under reset and initialization, and consider their impact to the application circuitry.

Table 2. Initial I/O States of UCD90xxx

DEVICE RESET I/O STATE
UCD90240 Hi-Z
UCD90320
UCD90320U
UCD90xxx FPWM pins are low, all other I/O pins are Hi-Z