For interleaved topologies like
Push-Pull, Half-Bridge, or Full-Bridge, twice as much FET switching frequency must
be used for calculations because the output inductor "sees" twice the FET switching
frequency.
Equation 59.
Duty cycle:
Equation 60.
DC-Gain:
Equation 61.
Sampling Gain Pole:
Equation 62.
Equation 63.
Equation 64.
N' is the turns ratio between auxiliary and primary winding.
Equation 65.
With Vslope:
Equation 66.
With SLM:
Equation 67.