SLVUBE6C November   2018  – July 2021 TPS56339

 

  1.   Trademarks
  2. 1Introduction
  3. 2Performance Specification Summary
  4. 3Modifications
    1. 3.1 Output Voltage Set Point
    2. 3.2 Adjustable UVLO
  5. 4EVM Photos
  6. 5Test Setup and Results
    1. 5.1  Input/Output Connections
    2. 5.2  Start-Up Procedure
    3. 5.3  Efficiency
    4. 5.4  Output Voltage Load Regulation
    5. 5.5  Output Voltage Line Regulation
    6. 5.6  Load Transients
    7. 5.7  Voltage Ripple
    8. 5.8  Powering Up
    9. 5.9  Powering Down
    10. 5.10 Output Short Protection and Recovery
    11. 5.11 Thermal Performance
  7. 6Board Layout
    1. 6.1 Layout
  8. 7Schematic and List of Materials
    1. 7.1 Schematic
    2. 7.2 List of Materials
  9. 8Revision History

5.8 Powering Up

Figure 5-10 and Figure 5-11 show the start-up waveforms for the TPS56339EVM. In Figure 5-10, the output voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor divider network. In Figure 5-11, the input voltage is initially applied and the output is inhibited by using a 3.3-V logic signal between EN and GND. When the EN voltage reaches the enable-threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of 5 V. The input voltage for these plots is 19 V and the load current is 3 A.

GUID-1C78D512-6A14-4DC1-BAC0-72BB4AAE5286-low.gifFigure 5-10 TPS56339EVM Startup Relative to VIN
GUID-71E44424-A26D-42E3-9536-C6A48DB20FEE-low.gifFigure 5-11 TPS56339EVM Startup Relative to Enable