The board layout for the TPS56C230EVM is shown in Figure 5-1 through Figure 5-5. The top and bottom layers are 2-oz copper thickness. Internal layers are 1-oz copper thickness.

The top layer contains the main power traces for VIN, VOUT and ground. Also on the top layer are connections for the pins of the TPS56C230 and a large area filled with ground. Most of the signal traces are located on the bottom left side, surrounding by a ground plane with an island for quiet analog ground that is connected to the main power ground at a single point. The internal layer-1 and internal layer-2 are dedicated ground planes. The bottom layer is another ground copper area with additional SW, VIN and VOUT copper fill. Ground traces on different layers are connected to each other with multiple vias placed on the board.

The input decoupling capacitors are located as close to the IC as possible. Critical analog circuits, such as the voltage set point divider, EN resister, SS capacitor, Mode resistor, VCC and AGND pin are terminated to quiet analog ground island on the top layer. The input and output connectors, test points and all of the components are located on the top side. The bottom layer is a ground plane along with the switching node copper fill, VIN and VOUT copper fill and the feedback trace from the point of regulation to the top of the resistor divider network.

Figure 5-1 TPS56C230EVM Top-Side Assembly

Figure 5-2 TPS56C230EVM Top-Side Layout

Figure 5-3 TPS56C230EVM Internal Layer-1 Layout

Figure 5-4 TPS56C230EVM Internal Layer-2 Layout

Figure 5-5 TPS56C230EVM Bottom Side Layout