SLVUBM5A April   2019  – August 2021 TPS54A24

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Performance Characteristics Summary
    3. 1.3 Modifications
      1. 1.3.1 Output Voltage Setpoint
      2. 1.3.2 Adjustable UVLO
      3. 1.3.3 Component Values to Evaluate Common Output Voltages
  3. 2Test Setup and Results
    1. 2.1  Input/Output Connections
    2. 2.2  Efficiency
    3. 2.3  Output Voltage Load Regulation
    4. 2.4  Load Transient and Loop Response
    5. 2.5  Output Voltage Ripple
    6. 2.6  Input Voltage Ripple
    7. 2.7  Powering Up
    8. 2.8  Powering Down
    9. 2.9  Start-Up Into Pre-Bias
    10. 2.10 Hiccup Mode Current Limit
    11. 2.11 Thermal Performance
  4. 3Board Layout
    1. 3.1 Layout
  5. 4Schematic and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 Bill of Materials
  6. 5Revision History

3.1 Layout

The board layout for the TPS54A24EVM-058 is shown in Figure 3-1 through Figure 3-6. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are
2-oz. copper.

The top layer contains the main power traces for VIN, VOUT, and SW. Also on the top layer are connections for the remaining pins of the TPS54A24 and the majority of the signal traces. The top layer has dedicated ground plane for quiet analog ground that is connected to the main power ground plane at a single point. The mid layer 1 is a large ground plane and also routes signals to test points. The mid layer 2 contains an additional large ground copper area with the BOOT trace and an additional VIN and VOUT copper fill. The bottom layer is another ground plane with the trace for the output voltage feedback and traces from signals to test points. The top-side ground traces are connected to the bottom and internal ground planes with multiple vias placed around the board.

The input decoupling capacitors and bootstrap capacitor are all located as close to the IC as possible. Additionally, the voltage set point resistor divider components are kept close to the IC. The voltage divider network ties to the output voltage at the point of regulation, the copper VOUT trace at the TP4 test point. An additional input bulk capacitor is used to limit the noise entering the converter from the input supply. Critical analog circuits such as the voltage set point divider, EN resistor, SS/TRK capacitor, RT/CLK resistor, and COMP pin are terminated to the quiet analog ground (AGND) island on the top layer.

Figure 3-1 Top-Side Composite View
Figure 3-3 Top Layer Layout
Figure 3-5 Mid Layer 2 Layout
Figure 3-2 Bottom-Side Composite View (Viewed From Bottom)
Figure 3-4 Mid Layer 1 Layout
Figure 3-6 Bottom Layer Layout