The board layout for the TPS543620EVM is shown in Figure 4-1 through Figure 4-6. The top-side layer of the EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper. The small size U1 circuit takes up an area of only approximately 100 mm² as shown on the silkscreen.

All of the required components for the TPS543620 are placed on the top layer. The input decoupling capacitors, BP5 capacitor, and bootstrap capacitor are all located as close to the IC as possible. Additionally, the voltage set point resistor divider components are kept close to the IC. An additional input bulk capacitor is used near the input terminal to limit the noise entering the converter from the supply used to power the board. Critical analog circuits such as the voltage set point divider, EN resistor, MODE resistor, and FSEL resistor are kept close to the IC and terminated to the quiet analog ground (AGND) island on the top layer.

The top layer contains the main power traces for VIN, VOUT, and SW. The top layer power traces are connected to the planes on other layers of the board with multiple vias placed around the board. There are multiple vias near the PGND pins of the IC to help maximize the thermal performance. Each TPS543620 circuit has its own dedicated ground are for quiet analog ground that is connected to the main power ground plane at a single point. This single point connection is done using vias to the internal ground planes. Lastly the voltage divider network ties to the output voltage at the point of regulation, the copper V_OUT area on the top layer.

The mid layer 1 is a large ground plane with as few traces as possible to minimize cuts in the ground plane. It is especially important to minimize cuts in the ground plane near the IC to help with minimize noise and maximize thermal performance.

The mid layer 2 contains a VIN copper area to connect both TPS543620 circuits to the input terminals. There is also a VIN copper area beneath each IC to connect its VIN pins together with a low impedance connection. This layer also has the trace to connect the FB divider to the output. Lastly, the remaining area of this layer is filled in with PGND.

The bottom layer is primarily used for another ground plane. This layer also has an additional VOUT copper area for the U2 circuit. Lastly, the load transient circuit is placed on this side of the EVM.

Figure 4-1 Top-Side Composite View

Figure 4-3 Top Layer Layout

Figure 4-5 Mid Layer 2 Layout

Figure 4-2 Bottom-Side Composite View (Viewed From Bottom)

Figure 4-4 Mid Layer 1 Layout

Figure 4-6 Bottom Layer Layout