SLVUBW7
May 2020
TPS7H4001QEVM-CVAL Evaluation Module User's Guide
Trademarks
1
TPS7H4001QEVM-CVAL Overview
1.1
Features
1.2
Applications
2
TPS7H4001QEVM-CVAL Default Configuration
3
TPS7H4001QEVM-CVAL Initial Setup
4
TPS7H4001QEVM-CVAL Testing
4.1
Output Voltage Regulation
4.2
Quadrature Phases
4.3
Output Voltage Ripple
4.4
Soft Startup
4.5
Transient Response to Positive/Negative Load Step (27 A to 67 A to 27 A)
4.6
Loop Frequency Response
4.7
Efficiency
4.8
Current Limiting
4.9
Current Sharing
5
TPS7H4001QEVM-CVAL EVM Schematic
6
TPS7H4001QEVM-CVAL Bill of Materials (BOM)
7
Board Layout
8
Appendix A
7
Board Layout
The following is the layer stack of the TPS7H4001QEVM-CVAL board.
Figure 23.
Top Overlay
Figure 24.
Top Solder
Figure 25.
Top Layer
Figure 26.
Signal Layer One
Figure 27.
Signal Layer Two
Figure 28.
Signal Layer Three
Figure 29.
Signal Layer Four
Figure 30.
Signal Layer Five
Figure 31.
Signal Layer Six
Figure 32.
Bottom Layer
Figure 33.
Bottom Solder
Figure 34.
Bottom Overlay