SLVUC05A November   2020  – July 2022 TPS25750

 

  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  2. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and Field Notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
      2. 1.3.2 Unique Address Interface Registers
  3. 2Unique Address Interface Register Detailed Descriptions
    1. 2.1  0x03 MODE Register
    2. 2.2  0x0D DEVICE_CAPABILITIES Register
    3. 2.3  0x14 - 0x19 INT_EVENT, INT_MASK, INT_CLEAR Registers
    4. 2.4  0x1A STATUS Register
    5. 2.5  0x26 POWER_PATH_STATUS Register
    6. 2.6  0x29 PORT_CONTROL Register
    7. 2.7  0x2D BOOT_STATUS Register
    8. 2.8  0x30 RX_SOURCE_CAPS Register
    9. 2.9  0x31 RX_SINK_CAPS Register
    10. 2.10 0x32 TX_SOURCE_CAPS Register
    11. 2.11 0x33 TX_SINK_CAPS Register
    12. 2.12 0x34 ACTIVE_CONTRACT_PDO Register
    13. 2.13 0x35 ACTIVE_CONTRACT_RDO Register
    14. 2.14 0x3F POWER_STATUS Register
    15. 2.15 0x40 PD_STATUS Register
    16. 2.16 GPIO Events
    17. 2.17 0x69 TYPEC_STATE Register
    18. 2.18 0x70 SLEEP_CONFIG Register
    19. 2.19 0x72 GPIO_STATUS Register
  4. 34CC Task Detailed Descriptions
    1. 3.1 Overview
    2. 3.2 PD Message Tasks
      1. 3.2.1 'SWSk' - PD PR_Swap to Sink
      2. 3.2.2 'SWSr' - PD PR_Swap to Source
      3. 3.2.3 'SWDF' - PD DR_Swap to DFP
      4. 3.2.4 'SWUF' - PD DR_Swap to UFP
      5. 3.2.5 'GSkC' - PD Get Sink Capabilities
      6. 3.2.6 'GSrC' - PD Get Source Capabilities
      7. 3.2.7 'SSrC' - PD Send Source Capabilities
    3. 3.3 Patch Bundle Update Tasks
      1. 3.3.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 3.3.2 'PBMc' - Patch Burst Mode Download Complete
      3. 3.3.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 3.3.4 Patch Burst Mode Example
      5. 3.3.5 'GO2P' - Go to Patch Mode
    4. 3.4 System Tasks
      1. 3.4.1 'DBfg' - Clear Dead Battery Flag
      2. 3.4.2 'I2Cr' - I2C Read Transaction
      3. 3.4.3 'I2Cw' - I2C Write Transaction
  5. 4User Reference
    1. 4.1 PD Controller Application Customization
    2. 4.2 Loading a Patch Bundle
  6. 5Revision History

1.3.2 Unique Address Interface Registers

The PD Controller supports Unique Address Interface registers (Unique Address Registers) provided in Table 1-1. Unless otherwise indicated, 2 or 4-byte registers are little endian (least significant byte in Data Byte 1). Registers that use four character codes (4CC) are defined where the first character corresponds to the ASCII value of Data Byte 1, the second character corresponds to the ASCII value of Data Byte 2, and so forth. Any 4CC codes that are less than 4 characters pad the tail with spaces (0x20).

For registers that are marked as not unique, the host may read that register using either slave address and it reads back the same value. For registers that are marked as not unique, the host may write that register using either slave address .

In the register map below, only the registers addresses shown are implemented. All other register addresses are Read-Only Reserved registers that must be ignored.

Table 1-1 Unique Address Interface Registers
Register Number(1)Register NameAccess# Data BytesUnique per PortDescription
0x02 Reserved
0x03 MODE RO 4 no Indicates the operational state of the port. The PD controller has limited functionality in some modes. See Section 2.1
0x04 TYPE RO 4 no Default response is 'I2C ' (note space as 4th character).
0x06 CUSTUSE RO 8 yes These 8 bytes are allocated for customer use as needed. The PD controller does not use this register. This register may be changed during application customization.
0x07 Reserved
0x08 CMD1 RW 4 yes Command register for the primary command interface. Cleared to 0x0000_0000 by the PD Controller during initialization and after successful processing of every command. If an unrecognized command is written to this register, it is replaced by a 4CC value of "!CMD".
0x09 DATA1 RW 64 yes Data register for the primary command interface (CMD1).
0x0A-0x0C Reserved
0x0D DEVICE_CAPABILITIES RO 4 no Description of supported features. See Section 2.2
0x0E Reserved
0x0F VERSION RO 4 no Binary Coded Decimal version number, bootloader/application code version. Represented as VVVV.MM.RR with leading 0's removed.e.g. 65794d (decimal) to 0x00010102 to 0001.01.02 to 1.1.2 (version). The version information is returned in little Endian format i.e. byte 1 = RR, byte 2 = MM, etc. The 16-bit field RR is used as the FW version in the Source Capabilities Extended and Sink Capabilities Extended messages.
0x10-0x13 Reserved
0x14 INT_EVENT1 RO 11 yes Interrupt event bit field for I2Cs_IRQ. If any bit in this register is 1, then the I2Cs_IRQ pin is pulled low. See Section 2.3
0x15 Reserved
0x16 INT_MASK1 RW 11 yes Interrupt mask bit field for INT_EVENT1. A bit in INT_EVENT1 cannot be set if it is cleared in this register. See Section 2.3
0x17 Reserved
0x18 INT_CLEAR1 RW 11 yes Interrupt clear bit field for INT_EVENT1. Bits set in this register are cleared from INT_EVENT1. See Section 2.3
0x19 Reserved
0x1A STATUS RO 5 yes Status bit field for non-interrupt events. See Section 2.4
0x1B-0x25 Reserved
0x26 POWER_PATH_STATUS RO 5 no Power Path Status. See Section 2.5
0x27-0x28 Reserved
0x29 PORT_CONTROL RW 4 yes Configuration bits affecting system policy. These bits may change during normal operation and are used for controlling the respective port. The PD Controller does not take immediate action upon writing. Changes made to this register take effect the next time the appropriate policy is invoked. Initialized by Application Customization. See Section 2.6
0x2A-0x2C Reserved
0x2D BOOT_STATUS RO 5 no Detailed status of boot process. This register provides details on PD Controller boot flags, Customer OTP configuration, and silicon revision See Section 2.7
0x2E BUILD_DESCRIPTION RO 49 no Build description. This is an ASCII string that uniquely identifies custom build information.
0x2F DEVICE_INFO RO 40 no Device information. This is an ASCII string with hardware and firmware version information of the PD Controller.
0x30 RX_SOURCE_CAPS RO 29 yes Received Source Capabilties. This register stores latest Source Capabilities message received over BMC. See Section 2.8
0x31 RX_SINK_CAPS RO 29 yes Received Sink Capabilities. This register stores latest Sink Capabilities message received over BMC. See Section 2.9
0x32 TX_SOURCE_CAPS RW 31 yes Source Capabilities for sending. This register stores PDOs and settings for outgoing Source Capabilities PD messages. Initialized by Application Customization. See Section 2.10
0x33 TX_SINK_CAPS RW 29 yes Sink Capabilities for sending. This register stores PDOs for outgoing Sink Capabilities USB PD messages. Initialized by Application Customization. See Section 2.11
0x34 ACTIVE_CONTRACT_PDO RO 6 yes Power data object for active contract. This register stores PDO data for the current explicit USB PD contract, or all zeroes if no contract. See Section 2.12
0x35 ACTIVE_CONTRACT_RDO RO 4 yes Power data object for the active contract. This register stores the RDO of the current explicit USB PD contract, or all zeroes if no contract. See Section 2.13
0x36-0x3E Reserved
0x3F POWER_STATUS RO 2 yes Details about the power of the connection. This register reports status regarding the power of the connection. See Section 2.14
0x40 PD_STATUS RO 4 yes Status of PD and Type-C state-machine. This register contains details regarding the status of PD messages and the Type-C state machine. See Section 2.15
0x41-0x68 Reserved
0x69 TYPEC_STATE RO 4 yes Contains current status of both CCn pins. See Section 2.17
0x6A-0x71 Reserved
0x72 GPIO_STATUS RO 8 no Captures status and settings of all GPIO pins. See Section 2.19
0x73-0x7E Reserved
(1) Any register number not shown is reserved for proprietary use.

The PD Controller implements the Unique Address Interface Tasks defined in Table 1-1.

Table 1-2 Unique Address Interface Tasks
Command 4CCTypeCommand SummaryReferences
PBMsPatch Bundle UpdateStart Patch Burst Download SequenceSee Section 3.3.1
PBMcPatch Bundle UpdatePatch Burst Download CompleteSee Section 3.3.2
PBMePatch Bundle UpdatePatch Burst Mode ExitSee Section 3.3.3
GO2PPatch Bundle UpdateForces PD controller to return to 'PTCH' mode and wait for patch over I2C.See Section 3.3.5
GSkCPD MessagePD Get Sink CapabilitiesSee Section 3.2.5
GSrCPD MessagePD Get Source CapabilitiesSee Section 3.2.6
SSrCPD MessagePD Send Source CapabilitiesSee Section 3.2.7
SWDFPD MessagePD DR_Swap to DFPSee Section 3.2.3
SWSkPD MessagePD PR_Swap to SinkSee Section 3.2.1
SWSrPD MessagePD PR_Swap to SourceSee Section 3.2.2
SWUFPD MessagePD DR_Swap to UFPSee Section 3.2.4
DBfgSystemClear Dead Battery FlagSee Section 3.4.1
I2CrSystemExecutes I2C read transaction on I2Cm.See Section 3.4.2
I2CwSystemExecutes I2C write transaction on I2Cm.See Section 3.4.3