SLVUC07A December   2020  – May 2021 TPS543320

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Background
    2. 1.2 Before You Begin
    3. 1.3 Performance Characteristics Summary
  3. 2Configurations and Modifications
    1. 2.1 Output Voltage
    2. 2.2 Switching Frequency (FSEL Pin)
    3. 2.3 Current Limit, Soft-Start Time, and Internal Compensation (MODE Pin)
    4. 2.4 Adjustable UVLO
  4. 3Test Setup and Results
    1. 3.1  Input/Output Connections
    2. 3.2  Efficiency
    3. 3.3  Output Voltage Regulation
    4. 3.4  Load Transient and Loop Response
    5. 3.5  Output Voltage Ripple
    6. 3.6  Input Voltage Ripple
    7. 3.7  Synchronizing to a Clock
    8. 3.8  Start-up and Shutdown with EN
    9. 3.9  Start-up and Shutdown with VIN
    10. 3.10 Hiccup Current Limit
    11. 3.11 Overvoltage Protection
    12. 3.12 Thermal Performance
  5. 4Board Layout
    1. 4.1 Layout
  6. 5Schematic and Bill of Materials
    1. 5.1 Schematic
    2. 5.2 Bill of Materials
  7. 6Revision History

3.1 Input/Output Connections

The TPS543320EVM is provided with input connectors, output connectors, and test points as shown in Table 3-1 and Table 3-2.

To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power supply capable of supplying greater than 3 A must be connected to J8 through a pair of 20-AWG wires or better. Banana jacks J5 and J9 provide an alternative connection to input power supply.

For U1, the load must be connected to J2 and for U2, the load must be connected to J7. A pair of 20-AWG wires or better must be used for each connection. With the maximum current limit setting, the maximum load current capability is near 5 A before the TPS543320 goes into current limit. Wire lengths must be minimized to reduce losses in the wires.

Test point TP11 provides a place to monitor the VIN input voltage with TP19 providing a convenient ground reference. TP2 is used to monitor the output voltage of U1 with TP5 as the ground reference. TP15 is used to monitor the output voltage of U2 with TP17 as the ground reference.

If modifications are made to the TPS543320EVM, the input current may change. The input power supply and wires connecting the EVM to the power supply must be rated for the input current.

Note:

For the FSEL pin of the TPS543320 to detect and set the correct switching frequency, the pin must either detect the resistor to ground or an external clock must applied to the pin before enabling the regulator. If starting up without an external clock, to properly detect the FSEL resistor value connected to ground, the buffers on the EVM need to be in high impedance mode. The shunts on J15 and J16 must be removed to put the buffers in high impedance mode for startup without an external clock.

Table 3-1 Connectors and Jumpers
REFERENCE DESIGNATOR NAME RELATED IC FUNCTION
J2 VOUT U1 VOUT screw terminal to connect load to output
J4 EN_OFF U1 2-pin header for enable. Add shunt to connect EN to ground and disable device.
J5, J9 VIN Both Banana jack for positive terminal and negative terminal of input power supply
J7 VOUT U2 VOUT screw terminal to connect load to output
J8 VIN Both VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)
J11 RDIV_VIN U2 2-pin header for enable divider. Remove shunt to disconnect EN pin divider for U2 from VIN. If J11 shunt is removed and J13 shunt is populated, U2 EN pin is pulled to ground through bottom resistor in divider disabling U2.
J13 EN_RDIV U2 2-pin header to connect enable divider to U2. Remove shunt to float EN pin of U2 to use internal UVLO to enable U2.
J14 VOUT Select U2 VOUT selection header. Use shunt to set output voltage. See Table 2-1.
J15 ENSYNC_U1 U1 2-pin header to connect U1 buffer output enable to ground. Populate shunt to enable output of buffer. Remove shunt to make buffer output high impedance.
J16 ENSYNC_U2 U2 2-pin header to connect U2 buffer output enable to ground. Populate shunt to enable output of buffer. Remove shunt to make buffer output high impedance.
J17 FSEL Select U2 FSEL selection header. Use shunt to select FSEL resistor. See Table 2-2.
J18 MODE Select U2 MODE selection header. Use shunt to select MODE resistor. See Table 2-3.
Table 3-2 Test Points
REFERENCE DESIGNATOR NAME RELATED IC FUNCTION
TP1 VIN_U1 U1 VIN test point. Use this for efficiency measurements.
TP2 VOUT_U1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP3 SW_U1 U1 SW node solder mask opening
TP4 PGND_U1 U1 PGND test point
TP5 PGND_EFF_U1 U1 PGND test point. Use this for efficiency measurements.
TP6 PGOOD_U1 U1 PGOOD test point
TP7 EN_U1 U1 EN test point. If applying an external voltage, it must be kept below the absolute maximum voltage of the EN pin of 6 V.
TP8 AGND_U1 U1 AGND test point
TP9 BODE_U1 U1 Test point between voltage divider network and output voltage. Used for Bode plot measurements.
TP10 VOUT_U1 U1 SMB connector to measure output voltage. When using this test point, the scope should be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP11 VIN Both VIN test point near input terminals
TP12 VIN_U2 U2 VIN test point. Use this for efficiency measurements.
TP13 SW_U2 U2 SW node solder mask opening
TP14 SW_U2 U2 SW node test point
TP15 VOUT_U2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot measurements.
TP16 PGND_U2 U2 PGND test point
TP17 PGND_EFF_U2 U2 PGND test point. Use this for efficiency measurements.
TP18 PGOOD_U2 U2 PGOOD test point
TP19 PGND Both PGND test point near input terminals
TP20 AGND_U2 U2 AGND test point
TP21 BP5_U2 U2 BP5 test point
TP22 BODE_U2 U2 Test point between voltage divider network and output voltage. Used for Bode plot measurements.
TP23 EN_U2 U2 EN test point. If you are applying an external voltage, it must be kept below the absolute maximum voltage of the EN pin of 6 V.
TP24 VO_ADJ U2 Test point for injecting current into the FB divider to adjust the DC output voltage or inject a step to FB to test OVP
TP25 VO_2NDSTG U2 Test point to measure output voltage after second stage filter if added to EVM.
TP26 SYNC Both SYNC test point. Supply an external clock to this test point to synchronize both regulators to it.
TP27 FSEL U2 FSEL test point
TP28 SW_U2 U2 SMB connector to measure SW node. When using this test point, the scope should be set for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series resistance creates a 10:1 attenuation.
TP29 VOUT_U2 U2 SMB connector to measure output voltage. When using this test point, the scope should be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP30 VO_2NDSTG U2 SMB connector to measure output voltage after second stage filter if added to EVM. When using this test point, the scope should be set for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is created.
TP31 FGEN Both Test point to connect function generator to load transient circuit. Slowly increase amplitude and vary slew rate of function generator for desired load step.
TP32 ISNS Both Test point to measure current in load transient circuit. Gain is 10 A/V.
TP33 PGND Both PGND test point for load transient circuit
TP34 MODE U2 MODE test point